Lines Matching full:intel
60 - [24.1-rc4] fatal error: intel/dev/intel_wa.h: No such file or directory
76 - mesa 24 intel A770 KOTOR black shadow smoke scenes
79 - Graphical glitches in RPCS3 after updating Vulkan Intel drivers
105 - intel: Require 64KB alignment when using CCS and multiple engines
108 - intel-clc build failure, i think?
127 - intel/fs: regression on MTL with 64bit values in UBO
139 - intel/meson: Make intel_stub_gpu work with \`meson devenv`
148 - [intel] mesa ftbfs with time_t64
154 - intel: all workarounds disabled with ATS skus
169 - [intel][anv][build][regression] - genX_grl.h:27:10: fatal error: grl/grl_cl_kernel.h: No such fil…
183 - Intel/anv: Allow pre-compiled shader caches to be reused across multiple devices
187 - intel: build failures
189 - i386 intel build failure: meson.build:45:6: ERROR: Unknown variable "prog_intel_clc".
198 - Dying Light native artifacts on Intel A770
217 - Palworld fails to launch on Intel Arc unless "force_vk_vendor" is set to "-1".
226 - The Finals fails to launch with DX12 on Intel Arc unless "force_vk_vendor" is set to -1.
928 - intel/compiler/xe2: Implement instruction compaction for DPAS.
929 - intel/compiler: Add couple of tests for fs_combine_constants
930 - intel/compiler: Fix rebuilding the CFG in fs_combine_constants
931 - intel: Use an intel enum for cmat scope
932 - intel/compiler: Enable lower_rotate_to_shuffle in subgroup lowering
939 - intel/compiler: Rename brw_image_param to isl_image_param
940 - intel/compiler: Rename BRW_WM_MSAA_* enums to INTEL_MSAA_*
941 - intel/compiler: Rename BRW_TESS_* enums to INTEL_TESS_*
942 - intel/compiler: Rename DISPATCH_MODE_* enums to INTEL_DISPATCH_MODE_*
943 - intel/compiler: Rename brw_vue_map to intel_vue_map
944 - intel/compiler: Rename brw_cs_dispatch_info to intel_cs_dispatch_info
945 - intel/compiler: Move disassemble functions to own header file
946 - intel/compiler: Include brw_disasm_info.h where its used
947 - intel/compiler: Merge intel_disasm.[ch] into corresponding brw files
948 - intel: Rename i965_{asm,disasm} tools to brw_{asm,disasm}
949 - intel/blorp: Don't require specific prog_data type in callback
950 - intel/blorp: Remove brw\_ prefix when not applicable
951 - intel/blorp: Simplify blorp_compile_fs() interface
952 - intel/blorp: Simplify blorp_compile_cs() interface
953 - intel/blorp: Use a struct to return blorp_compile_*() results
954 - intel/blorp: Remove outdated reference in comment
955 - intel/blorp: Move brw_blorp_get_urb_length helper
956 - intel/blorp: Avoid brw types in blorp_priv.h
957 - intel/blorp: Move brw_compiler.h include to where is needed
958 - intel/blorp: Use a Meson dependency for blorp
959 - intel: Add missing dependencies on blorp
960 - intel/decoder: Move decoder to a separate module
961 - intel/compiler: Collect NIR-only passes in intel_nir.h
962 - intel/compiler: Rename the passes and files related to intel_nir.h
963 - intel/compiler: Rename brw_gfx_ver_enum.h to intel_gfx_ver_enum.h
964 - intel: Remove brw\_ prefix from process debug function
965 - intel/isl: Include compiler generic header
968 - intel/compiler: Use "intel" prefix for walk_order enum
980 - intel/meson: Remove usage of meson.source_root and meson.build_root
981 - intel/meson: Fix warning about broken str.format
982 - intel/elk: Fork Gfx8- compiler by copying existing code
983 - intel/elk: Compile ELK library, tests and tools
984 - intel/elk: Remove compiler specific devinfo hash
985 - intel/elk: Remove a bunch of files that don't apply for Gfx8-
986 - intel/elk: Use common code in intel/compiler
987 - intel/elk: Remove stages not used in Gfx8-
988 - intel/elk: Remove DPAS lowering
989 - intel/elk: Rename files to use elk prefix
990 - intel/elk: Rename header guards
991 - intel/elk: Update doxygen-like file comments
992 - intel/elk: Rename C++ namespace
993 - intel/elk: Rename symbols
994 - intel/elk: Don't include elk_eu_defines.h in elk_nir.h
995 - intel/elk: Create separate header for opcodes
996 - intel/blorp: Move brw specific code to a separate file
997 - intel/blorp: Explicitly include brw_compiler.h header
998 - intel/blorp: Add ELK support
999 - intel/blorp: Remove Gfx9+ references in elk code
1000 - intel/decoder: Add ELK support
1005 - intel/tools: Add ELK support for aubinator
1006 - intel/tools: Add ELK support for aubinator_error_decode
1007 - intel/tools: Add ELK support for intel_hang_replay
1008 - intel/tools: Add ELK support for aubinator_viewer
1009 - intel/tools: Add ELK support for intel_hang_viewer
1010 - intel: Use _brw suffix for genX headers that rely on brw
1011 - intel/meson: Rename libintel_compiler to libintel_compiler_brw
1012 - intel/tools: Add extra compiler device sha only for Gfx9+
1013 - intel/elk: Move nir_options to its own c/h file pair
1014 - intel-clc: Use correct set of nir_options when building for Gfx8
1015 - intel/elk: Use anonymous namespace in fs_combine_constants
1016 - intel/elk: Remove tests for Gfx9+
1017 - intel/brw: Remove assembler tests for Gfx8-
1018 - intel/brw: Remove EU compaction tests for Gfx8-
1019 - intel/brw: Remove EU validation tests for Gfx8-
1020 - intel/brw: Remove pass test cases for Gfx8-
1021 - intel/brw: Assert Gfx9+
1022 - intel/compiler: Remove has_render_target_reads from wm_prog_data
1023 - intel/brw: Remove Gfx8- passes from optimize()
1024 - intel/brw: Pull opt_copy_propagation out of fs_visitor
1025 - intel/brw: Pull opt_cmod_propagation out of fs_visitor
1026 - intel/brw: Pull opt_saturate_propagation out of fs_visitor
1027 - intel/brw: Pull dead_code_eliminate out of fs_visitor
1028 - intel/brw: Pull opt_combine_constants out of fs_visitor
1029 - intel/brw: Pull opt_cse out of fs_visitor
1030 - intel/brw: Pull bank_conflicts out of fs_visitor
1031 - intel/brw: Pull peephole_sel out of fs_visitor
1032 - intel/brw: Pull redundant_halt out of fs_visitor
1033 - intel/brw: Pull opt_algebraic out of fs_visitor
1034 - intel/brw: Pull split/compact virtual_grf opts out of fs_visitor
1035 - intel/brw: Pull opt_split_sends out of fs_visitor
1036 - intel/brw: Pull opt_zero_samples out of fs_visitor
1037 - intel/brw: Pull eliminate_find_live_channel out of fs_visitor
1038 - intel/brw: Pull remove_extra_rounding_modes out of fs_visitor
1039 - intel/brw: Pull register_coalesce out of fs_visitor
1040 - intel/brw: Pull lower_constant_loads out of fs_visitor
1041 - intel/brw: Pull lower_pack out of fs_visitor
1042 - intel/brw: Pull lower_simd_width out of fs_visitor
1043 - intel/brw: Pull lower_barycentrics out of fs_visitor
1044 - intel/brw: Pull lower_logical_sends out of fs_visitor
1045 - intel/brw: Pull fixup_nomask_control_flow out of fs_visitor
1046 - intel/brw: Pull lower_integer_multiplication out of fs_visitor
1047 - intel/brw: Pull lower_sub_sat out of fs_visitor
1048 - intel/brw: Pull lower_derivatives out of fs_visitor
1049 - intel/brw: Pull lower_regioning out of fs_visitor
1050 - intel/brw: Pull fixup_sends_duplicate_payload out of fs_visitor
1051 - intel/brw: Pull lower_uniform_pull_constant_loads out of fs_visitor
1052 - intel/brw: Pull lower_find_live_channel out of fs_visitor
1053 - intel/brw: Pull lower_load_payload out of fs_visitor
1054 - intel/brw: Use references for a couple of backend_shader passes
1055 - intel/brw: Simplify OPT macro usage in fs_visitor::optimize
1056 - intel/brw: Pull fixup_3src_null_dest out of fs_visitor
1057 - intel/brw: Pull emit_dummy_memory_fence_before_eot out of fs_visitor
1058 - intel/brw: Pull emit_dummy_mov_instruction out of fs_visitor
1059 - intel/brw: Pull lower_scoreboard out of fs_visitor
1060 - intel/brw: Pull optimize() out of fs_visitor
1061 - intel/brw: Move optimize and small optimizations to brw_fs_opt.cpp
1062 - intel/brw: Move virtual GRF opts into their own file
1063 - intel/brw: Move fs algebraic to its own file
1064 - intel/brw: Move small lowering passes into brw_fs_lower.cpp
1065 - intel/brw: Move lower_integer_multiplication to its own file
1066 - intel/brw: Expose flag_mask/bit_mask fs helpers
1067 - intel/brw: Move lower_simd_width to its own file
1068 - intel/brw: Move workarounds to a separate file
1069 - intel/blorp: Remove Gfx8- references in BRW code
1070 - intel/brw: Move brw_compile_* functions out of vec4-specific files
1071 - intel/brw: Move type_size_* functions out of vec4-specific file
1072 - intel/brw: Always use scalar shaders
1073 - intel/brw: Remove vec4 backend
1074 - intel/brw: Remove now unused vec4-only opcodes
1075 - intel/brw: Remove unused legacy shader stages
1076 - intel/brw: Remove Gfx8- code from disassembler
1077 - intel/brw: Remove Gfx8- code from assembler
1078 - intel/brw: Remove Gfx8- code from brw_compile_* functions
1079 - intel/brw: Remove Gfx8- code from scheduler
1080 - intel/brw: Remove Gfx8- code from register allocator
1081 - intel/brw: Remove Gfx8- code from thread payload
1082 - intel/brw: Remove Gfx8- code from NIR conversion
1083 - intel/brw: Remove Gfx8- code from lower storage image pass
1084 - intel/brw: Remove Gfx8- code from lower logical sends
1085 - intel/brw: Remove Gfx8- code from generator
1086 - intel/brw: Remove Gfx8- code from backend passes
1087 - intel/brw: Remove Gfx8- code from EU compaction
1088 - intel/brw: Remove Gfx8- code from IR performance analysis
1089 - intel/brw: Remove Gfx8- code from EU emission
1090 - intel/brw: Remove Gfx8- code from EU validation
1091 - intel/brw: Remove Gfx8- code from NIR passes
1092 - intel/brw: Remove Gfx4-5 manual compression selection
1093 - intel/brw: Remove Gfx8- code from EU codegen helpers
1094 - intel/brw: Remove Gfx8- code from NIR options
1095 - intel/brw: Remove Gfx8- code from register type helpers
1096 - intel/brw: Remove Gfx8- specific EU inst helpers
1097 - intel/brw: Remove Gfx8- code from inst FC and F macros
1098 - intel/brw: Replace inst F8 macro with F macro
1099 - intel/brw: Remove Gfx8- code from inst F20 macros
1100 - intel/brw: Remove Gfx8- code from inst FD20 and FV20 macros
1101 - intel/brw: Remove Gfx8- code from inst FI macros
1102 - intel/brw: Remove Gfx8- code from inst BRW_IA*_ADDR_IMM macros
1103 - intel/brw: Remove Gfx8- code from inst FFDC, FDC and FD macros
1104 - intel/brw: Update comments for FK macro
1105 - intel/brw: Replace inst FF macro with F or F20 macros
1106 - intel/brw: Remove F16TO32 and F32TO16 opcodes
1107 - intel/brw: Remove Gfx8- code from builder
1108 - intel/brw: Remove Gfx8- code from fs_inst
1109 - intel/brw: Remove Gfx8- code from VUE map
1110 - intel/brw: Remove Gfx8- code from SIMD lowering
1111 - intel/brw: Remove Gfx8- code from visitor
1112 - intel/brw: Remove Gfx8- remaining opcodes
1113 - intel/brw: Remove MRF type
1114 - intel/brw: Inline brw_nir_apply_sampler_key code
1115 - intel/brw: Remove unused attrib workarounds
1116 - intel/brw: Remove edgeflag_is_last VS parameter
1117 - intel/brw: Remove Gfx8- fields from \*_prog_key structs
1118 - intel/brw: Remove Gfx8- fields from \*_prog_data structs
1119 - intel/brw: Use a single register set
1120 - intel/brw: Remove runtime_check_aads_emit
1121 - intel/brw: Remove automatic_exec_sizes
1122 - intel/brw: Use fs_visitor instead of backend_shader in various passes
1123 - intel/brw: Fold fs_instruction_scheduler into instruction_scheduler
1124 - intel/brw: Change cfg_t to refer to fs_visitor
1125 - intel/brw: Move dump_* functions into fs_visitor
1126 - intel/brw: Fold backend_shader into fs_visitor
1127 - intel/brw: Remove extra stage_prog_data field in fs_visitor
1128 - intel/brw: Remove brw_shader.h
1129 - intel/meson: Add dependencies for brw and elk
1130 - intel/compiler: Remove nir_print_instr hack in disasm_info
1131 - intel/brw: Use C++ for brw_disasm_info.c
1132 - intel/brw: Hide the definition of cfg_t et al from C code
1133 - intel/brw: Use fs_inst in cfg_t
1134 - intel/brw: Use fs_inst explicitly in various passes
1135 - intel/brw: Use fs_inst in disasm_annotate()
1136 - intel/brw: Move functions from backend_instruction into fs_inst
1137 - intel/brw: Fold backend_instruction into fs_inst
1138 - intel/brw: Remove typedefs from fs_builder
1139 - intel/brw: Fold backend_reg into fs_reg
1140 - intel/brw: Simplify usage of reg immediate helpers
1141 - intel/compiler: Fix SIMD lowering when instruction needs a larger SIMD
1142 - intel/elk: Remove split sends
1143 - intel/elk: Remove DPAS opcode
1144 - intel/elk: Remove BTD and RT opcodes
1145 - intel/elk: Remove DP4A opcode
1146 - intel/elk: Remove ROR and ROL opcodes
1147 - intel/elk: Remove IADD3 opcode
1148 - intel/elk: Remove EU compaction logic for Gfx9+
1149 - intel/elk: Remove encoding for Gfx9+
1150 - intel/elk: Remove SYNC opcode and SWSB annotations
1151 - intel/elk: Remove Gfx12 SFIDs and related LSC code
1152 - intel/elk: Remove Gfx9+ sampler messages and modes
1153 - intel/elk: Rename symbols for A64 OWord Block R/W messages
1154 - intel/elk: Remove Gfx9+ dataport messages
1155 - intel/elk: Remove FB_READ opcodes
1156 - intel/elk: Remove Gfx12.5 URB message
1157 - intel/elk: Remove ex_desc and ex_mlen from elk_inst
1158 - intel/elk: Remove Xe2 logical sends lowering
1159 - intel/elk: Remove unused sources from ELK_SHADER_OPCODE_SEND
1160 - intel/elk: Remove unused SEND features
1161 - intel/elk: Remove validation code for Gfx9+
1162 - intel/elk: Remove Gfx9+ from nir conversion
1163 - intel/elk: Remove Gfx9+ from compile/run functions
1164 - intel/elk: Remove FB_WRITE_LOGICAL_SRC_SRC_STENCIL
1165 - intel/elk: Remove Gfx9+ from passes
1166 - intel/elk: Remove Gfx9+ from thread payload
1167 - intel/elk: Remove Gfx9+ from EU emission
1168 - intel/elk: Remove coarse pixel handling
1169 - intel/elk: Remove Gfx9+ from FS generator
1170 - intel/elk: Remove Gfx9+ from Reg related code
1171 - intel/elk: Remove Gfx9+ from asm grammar
1172 - intel/elk: Remove Gfx9+ from disasm
1173 - intel/elk: Remove Gfx9+ from NIR auxiliary code
1174 - intel/elk: Remove use_tcs_multi_patch
1175 - intel/elk: Remove Gfx9+-only passes
1176 - intel/elk: Remove uses of intel_device_info_is_9lp()
1177 - intel/elk: Remove remaining Gfx9+ code
1178 - intel/elk: Remove multi-polygon support
1179 - intel/elk: Clean up unused code in elk_compiler.h
1180 - intel/brw: Use hstride instead of stride for accumulator
1181 - intel/brw: Use helper to create accumulator register
1182 - intel/brw: Fix validation of accumulator register
1184 - intel/tools: Make intel_stub_gpu work when using meson devenv
1185 - intel/brw: Implement quad_vote_any and quad_vote_all
1186 - intel/brw: Use predicates for quad_vote_any and quad_vote_all when available
1188 - intel/brw: Handle Xe2 in brw_fs_opt_zero_samples
1189 - intel/brw: Remove vestiges of sources on IF opcode, only valid on Gfx6
1190 - intel/brw: Add a src array for the common case in fs_inst
1191 - intel/brw: Refactor FS validation macros
1192 - intel/brw: Remove two duplicated validate calls in optimizer
1193 - intel/brw: Move validate out of fs_visitor
1194 - intel/brw: Support FIXED_GRF when generating code for CLUSTER_BROADCAST
1195 - intel/brw: Lower VGRFs to FIXED_GRFs earlier
1688 - ci/intel: decompose anv-tgl-test so we can specify custom devices for TGL
1689 - ci/intel: add acer-cp514-2h-11{30,60}g7-volteer
1690 - ci/intel: move machine definition to the intel-tgl-skqp job
1691 - ci/intel: split asus-cx9400-volteer into acer-cp514-2h-11{30,60}g7-volteer
1693 - intel/tools: avoid invalid time and file bits combination
1720 - ci/intel: sona device_type is back online
1806 - intel/vulkan: assume() that we don't use "ISL_NUM_FORMATS"
1807 - intel/hasvk: assume() we don't get ISL_NUM_FORMATS
1808 - meson: drop intel-cl deprecation of 'false'
1809 - meson: rework intel-rt option to be a feature
1810 - meson: Allow building intel-clc for the host if it can be run
1811 - intel/brw: track last successful pass and leave the loop early
2350 - nvk: Stop pretending to handle Intel image intrinsics
2471 - driconf: Change vendorid on Palworld for Intel
2474 - driconf: add SotTR DX12 to Intel XeSS workaround
2476 - intel/ds: add pipe control reasons to perfetto flushes
2480 - intel/fs: Use full 32-bit sample masks when immediate.
2481 - intel/eu/validate: SEND instructions don't have immediate encodings on Gen12+.
2482 - intel/eu/gfx12.5+: Don't fail validation with ARF register restriction error for indirect address…
2483 - intel/compiler/xe2: Add Xe2 bounds to FF() macro.
2484 - intel/compiler/xe2: Implement codegen of general instruction controls.
2485 - intel/compiler/xe2: Implement codegen of 2-source instruction operands.
2486 - intel/compiler/xe2: Implement codegen of indirect immediates.
2487 - intel/compiler/xe2: Implement codegen of three-source instructions.
2488 - intel/compiler: Add assume() checks to brw_compact_inst_(set\_)bits().
2489 - intel/compiler/xe2: Implement codegen of compact instructions.
2490 - intel/compiler/xe2: Implement instruction compaction.
2491 - intel/compiler/xe2: Fix for NibCtrl field removal.
2492 - intel/compiler/xe2: Fix for the removal of most predication modes.
2493 - intel/compiler/xe2: Add extra flag registers.
2494 - intel/compiler/xe2: Fix for the removal of AccWrCtrl.
2495 - intel/ir/xe2+: Add support for 32 SBID tokens to performance model.
2496 - intel/fs/xe2+: Disable bank conflict mitigation pass for now.
2497 - intel/eu/xe2+: Translate brw_reg fields in REG_SIZE units to physical 512b GRF units during codeg…
2498 - intel/fs: Set the default execution group to 0 when not representable by the platform.
2499 - intel/fs: Emit QUAD_SWIZZLE instructions with WE_all for derivative lowering.
2500 - intel/fs/xe2+: Allow SIMD16 MULH instructions.
2501 - intel/brw/xe2: Render target reads have been removed from the hardware.
2502 - intel/brw/xe2+: Update encoding of FB write descriptor message control.
2503 - intel/brw/xe2+: Update encoding of FB write extended descriptor.
2504 - intel/brw/xe2+: Double allowed SIMD width of FB write SEND messages.
2505 - intel/brw/xe2+: Allow FS stencil output in SIMD16 dispatch mode.
2506 - intel/brw/xe2+: Allow dual-source blending in SIMD16 mode.
2507 - intel/blorp/xe2+: Don't use replicated-data clears.
2508 - intel/brw/gfx12: Setup PS thread payload registers required for ALU-based pixel interpolation.
2509 - intel/brw/xe2+: Setup PS thread payload registers required for ALU-based pixel interpolation.
2511 - intel/brw/xehp+: Replace lsc_msg_desc_dest_len()/lsc_msg_desc_src0_len() with helpers to do the c…
2512 - intel/eu/xehp+: Don't initialize mlen and rlen descriptor fields from lsc_msg_desc*().
2513 - intel/brw/xehp+: Drop redundant arguments of lsc_msg_desc*().
2514 - intel/fs/gfx20+: Implement sub-dword integer regioning restrictions.
2515 - intel/fs/gfx20+: Handle subdword integer regioning restrictions in copy propagation.
2849 - intel/compiler: Disable DPAS instructions on MTL
2850 - intel/compiler: Use u_foreach_bit64 in brw_get_compiler_config_value
2851 - intel/compiler: Track lower_dpas flag in brw_get_compiler_config_value
2852 - intel/compiler: Track mue_compaction and mue_header_packing flags in brw_get_compiler_config_value
2853 - intel/fs: Fix shift counts for 8- and 16-bit types
2854 - intel/rt: Don't directly generate umul_32x16
2855 - intel/compiler/xe2: Update get_sampler_lowered_simd_width
2856 - intel/fs: Move opcode modification before the switch that emits srcs
2857 - intel/compiler/xe2: Use new sample_*_mlod messages
2859 - intel/compiler/xe2: Emit texture instructions w/ combined LOD and array index
2860 - intel/compiler/xe2: Set SIMD mode for sampler messages
2862 - intel/fs: Delete stale comment in nir_intrinsic_ballot implementation
2864 - intel/fs: Enable nir_opt_uniform_atomics in all shader stages
2865 - intel/fs: Use constant of same type to write flag
2866 - intel/fs: Add fast path for ballot(true)
2868 - intel/fs: Use nir_opt_uniform_subgroup
2872 - intel/brw: Silence "statement may fall through" warning
2873 - intel/brw: Correctly dump subnr for FIXED_GRF in INTEL_DEBUG=optimizer
2874 - intel/compiler: Enforce 64-bit RepCtrl restriction in eu_validate
2875 - intel/brw: Integer multiply w/ DW and W sources is not commutative
2876 - intel/brw: Combine constants for src0 of integer multiply too
2877 - intel/brw: Combine constants for src0 of POW instructions too
2878 - intel/brw: Avoid a silly add with zero in assign_curb_setup
2879 - intel/fs: Don't allow 0 stride on MOV destination
2880 - intel/brw/xe2: Correctly disassemble RT write subtypes
2881 - intel/brw: Fix handling of accumulator register numbers
2882 - intel/brw: Allow SIMD16 F and HF type conversion moves
2883 - intel/brw: Remove last vestiges of could_coissue
2884 - intel/brw: Clear write_accumulator flag when changing the destination
2885 - intel/brw: Use enums for DPAS source regioning
2886 - nir: intel/brw: Change the order of sources for nir_dpas_intel
2887 - intel/brw/xe2+: DPAS must be SIMD16 now
2888 - intel/brw/xe2+: Use phys_nr and phys_subnr in DPAS encoding
2889 - intel/brw/xe2: Update brw_nir_analyze_ubo_ranges to account for 512b physical registers
2890 - intel/brw/xe2: Update uniform handling to account for 512b physical registers
2891 - intel/compiler: Ensure load_barycentric_at_sample and load_interpolated_input remain together
2892 - intel/brw: Don't call nir_opt_remove_phis before nir_convert_from_ssa
2893 - intel/elk: Don't call nir_opt_remove_phis before nir_convert_from_ssa
2894 - intel/brw: Delete stray nir_opt_dce
2895 - intel/elk: Delete stray nir_opt_dce
2896 - intel/brw/xe2+: Implement Wa 22016140776
2897 - intel/brw/xe2+: Only apply Wa 22016140776 to math instructions
2898 - intel/brw: Fix handling of cmat_signed_mask
2899 - nir: intel/brw: Remove cmat_signed_mask from dpas_intel intrinsic
2900 - intel/brw: Fix optimize_extract_to_float for i2f of unsigned extract
2901 - intel/elk: Fix optimize_extract_to_float for i2f of unsigned extract
2912 - intel/cmat: fix stride calculation in cmat load/store
2930 - docs: fix doc build 'intel/dev/intel_device_info_gen.h' file not found
3103 - intel/dev: update DG2 device names
3104 - intel/dev: update DG2 device names
3105 - intel/dev: update DG2 device names
3106 - intel/dev: 0x7d45 is mtl-u not mtl-h
3114 - intel/dev/common: Add xe2 support to get_l3_list()
3115 - intel/dev: Add ARL platform enums
3116 - intel/dev: Add intel_device_info_is_mtl_or_arl()
3117 - intel/l3: Define l3 config for ARL
3119 - intel/i915: ARL also supports the set-PAT uapi
3120 - intel/dev: Define engine prefetch for ARL
3123 - intel/compiler: Lower DPAS instructions on ARL except ARL-H
3126 - intel/dev: Add device info for ARL
3127 - intel/compiler: Set branch shader required-width as 16 for xe2
3128 - intel/compiler: Implement nir_intrinsic_load_topology_id_intel for xe2
3129 - intel/compiler: Verify SIMD16 is used for xe2 BTD/RT dispatch
3130 - intel/dev: Add 2 additional ADL-N PCI ids
3131 - intel/compiler: Adjust fs_visitor::emit_cs_terminate() for Xe2
3132 - intel/dev: Adjust device strings for ATS-M devices
3133 - intel/dev: Add ATS-M PCI ID for Data Center GPU Flex 170G
3134 - intel/compiler/fs: Restore SIMD32 restriction for ray_queries on Xe2
3135 - intel/compiler: nib_ctrl no longer exists on Xe2+
3136 - intel/dev/mesa_defs.json: Add LNL WA entries
3137 - intel/dev: Add 0x56be and 0x56bf DG2 PCI IDs
3138 - intel/dev: Change ATS-M 0x56c2 string from 170G to 170V
3139 - intel/brw: Avoid getting a stride of 0 for nir_intrinsic_exclusive_scan
3195 - intel/isl/xe2: Disable route of Sampler LD message to LSC
3197 - intel/genxml/xe2: Remove L3ALLOC
3198 - intel/dev: Reduce usage of intel_device_info_compute_system_memory()
3199 - intel: Make memory heaps consistent between KMDs
3204 - intel/common: Add functions to handle async vm bind
3209 - intel: Fix intel_get_mesh_urb_config()
3211 - intel/common: Fix location of C++ support macro in intel_gem.h
3212 - intel: Remove circular dependency between intel/dev and intel/common
3213 - intel/common: Add intel_engines_supported_count()
3216 - intel: Sync i915_drm.h
3217 - intel/common: Implement i915_engines_is_guc_semaphore_functional()
3218 - intel: Sync xe_drm.h
3219 - intel/common: Implement xe_engines_is_guc_semaphore_functional()
3227 - intel: Move intel_define.h to i915/intel_define.h
3228 - intel/common: Remove more i915_drm.h includes from common code
3229 - intel/tools/error_decode: Add function to try to open error dump file
3230 - intel/tools/error_decode: Simply error message handling
3231 - intel/tools/error_decode: Add support to search for Xe KMD error dumps
3232 - intel/tools/error_decode: Detect and split error dump file parsing by KMD
3233 - intel: Sync xe_drm.h
3236 - intel/tools/error_decode: Move code that can be shared between i915 and Xe error decoders
3237 - intel/tools/error_decode: Parse Xe KMD error dump file
3238 - intel/tools: Fix compilation in 32 bits
3239 - intel/nullhw: Fix 32bits compilation warnings
3245 - intel: Drop pre-production steppings
3247 - intel/dev: Nuke 'ver == 10' check
3248 - intel/dev: Nuke display_ver
3249 - intel: Enable Xe KMD support by default
3254 - intel/tools/error_decode: Fix parsing in Xe decoder
3255 - intel/tools/error_decode: Add function to print batch in Xe decoder
3256 - intel/tools/error_decode: Parse HW context in Xe decoder
3259 - intel/decoder: Fix binding table pointer entry being marked as invalid
3261 - intel/genxml: Add more instdone registers
3262 - intel/genxml/gfx125: Fix definition of INTERFACE_DESCRIPTOR_DATA::Thread group dispatch size
3263 - intel/genxml/xe2: Update definition of INTERFACE_DESCRIPTOR_DATA
3266 - intel/tools/error2hangdump: Print out_filename when failed to open it
3267 - intel/tools/error2hangdump: Replace drm_i915_gem_engine_class by intel_engine_class
3268 - intel/tools: Move Xe KMD error decode functions to a separated file
3269 - intel/tools: Move ascii85_decode_char() to error_decode_lib
3270 - intel/tools: Move more Xe KMD error decode functions to error_decode_xe_lib
3271 - intel/tools/error2hangdump: Move code that will be shared with Xe parser to error2hangdump_lib
3272 - intel/tools/error2hangdump: Move i915 parser to a function
3273 - intel/tools/error2hangdump: Add Xe KMD support
3278 - intel/tools/aubinator_error_decode: Move definition of option_color to header
3279 - intel/decoder: Add intel_print_group_custom_spacing()
3280 - intel/tools: Parse INSTDONE registers in Xe KMD error dump
3281 - intel: Sync xe_drm.h
3282 - intel/dev: Read GFX IP version during runtime
3441 - intel: Only build shaders with anv and iris
3477 - intel/dev: Fix typo (ajust -> adjust)
3479 - intel/nir: Pass devinfo and prog_data to brw_nir_lower_cs_intrinsics
3480 - intel: Add driver support for hardware generated local invocation IDs
3481 - intel: Use hardware generated compute shader local invocation IDs
3484 - intel/fs: Don't include sync.nop in instruction count statistics
3485 - intel/fs: Don't rely on CSE for VARYING_PULL_CONSTANT_LOAD
3486 - intel/brw: Delete enum brw_urb_write_flags
3487 - intel/brw: Delete more unused defines
3488 - intel/brw: Delete legacy SFIDs
3489 - intel/brw: Delete SIMD4x2 URB opcodes
3490 - intel/brw: Delete more unused compression stuff
3491 - intel/brw: Delete SINCOS
3492 - intel/brw: Delete constant_buffer_0_is_relative
3493 - intel/brw: Delete compiler->supports_shader_constants
3494 - intel/brw: Delete enum gfx6_gather_sampler_wa
3495 - intel/brw: Delete brw_wm_prog_key::line_aa
3496 - intel/brw: Delete unnecessary brw_wm_prog_data fields
3497 - intel/brw: Delete some swizzling functions
3498 - intel/brw: Delete brw_eu_util.c
3499 - intel/brw: Change unit tests to use TEX_LOGICAL instead of TEX
3500 - intel/brw: Delete SHADER_OPCODE_TXF_CMS[_LOGICAL]
3501 - intel/brw: Delete SHADER_OPCODE_TXF_UMS
3502 - intel/brw: Allow CSE on TXF_CMS_W_GFX12_LOGICAL
3503 - intel/brw: Delete legacy texture opcodes
3504 - intel/brw: Mark FIND[_LAST]_LIVE_CHANNEL as not writing the flag
3505 - intel/brw: Replace CS_OPCODE_CS_TERMINATE with SHADER_OPCODE_SEND
3506 - intel/brw: Avoid copy propagating any fixed registers into EOTs
3507 - intel/brw: Handle SHADER_OPCODE_SEND without src[3] in copy prop
3508 - intel/brw: Add assertions that EOT messages live in g112+
3509 - intel/brw: Copy the smaller payload in fixup_sends_duplicate_payload
3510 - intel/brw: Make register coalescing obey the g112-g127 restriction
3511 - intel/brw: Call constant combining after copy propagation/algebraic
3512 - intel/brw: Remove SIMD lowering to a larger SIMD size
3513 - intel/brw: Unindent code after previous change
3515 - intel/brw: Emit better code for read_invocation(x, constant)
3519 - intel/fs: Avoid generating useless UNDEFs for every SSA def
3520 - intel/brw: Split out 64-bit lowering from algebraic optimizations
3521 - intel/brw: Don't consider UNIFORM_PULL_CONSTANT_LOAD a send-from-GRF
3522 - intel/brw: Eliminate top-level FIND_LIVE_CHANNEL & BROADCAST once
3523 - intel/brw: Fix check for 64-bit SEL lowering types
3524 - intel/brw: Assert that min/max are not happening in 64-bit SEL lowering
3525 - intel/brw: Use correct execution pipe for lowering SEL on DF
3526 - intel/brw: Unify DF and Q/UQ lowering for MOV
3527 - Revert "intel/brw: Don't consider UNIFORM_PULL_CONSTANT_LOAD a send-from-GRF"
3528 - intel/brw: Fix opt_split_sends() to allow for FIXED_GRF send sources
3529 - intel/brw: Fix register coalescing's LOAD_PAYLOAD dst offset handling
3530 - intel/brw: Fix destination stride assertion in copy propagation
3531 - intel/brw: Allow changing types for LOAD_PAYLOAD with 1 source
3532 - intel/brw: Delete brw_fs_lower_minmax
3536 - intel/brw: Stop checking mlen on math opcodes in CSE pass
3537 - intel/brw: Rearrange fs_inst fields
3538 - intel/brw: Fix generate_mov_indirect to check has_64bit_int not float
3539 - intel/brw: Fix lower_regioning for BROADCAST, MOV_INDIRECT on Q types
3540 - intel/brw: Update comments for indirect MOV splitting
3541 - intel/brw: Don't mention gfx7 limitations in shuffle comments
3542 - intel/brw: Drop dead CHV checks.
3543 - intel/brw: Drop align16 support in brw_broadcast()
3544 - intel/brw: Drop gfx7 scratch message setup code
3545 - intel/brw: Delete if_depth_in_loop
3546 - intel/brw: Delete fs_visitor::vgrf helper
3547 - intel/brw: Drop default size of 1 from bld.vgrf() calls
3548 - intel/brw: Use SHADER_OPCODE_SEND for coherent framebuffer reads
3549 - intel/brw: Replace FS_OPCODE_LINTERP with BRW_OPCODE_PLN
3550 - intel/brw: Make an fs_builder::SYNC helper
3696 - intel/aux_map: fix fallback unmapping range on failure
3698 - intel/decoder: make vertex data decoding optional
3699 - intel/decoder: don't ignore BT entries at offset 0
3700 - intel/genxml: add CCS_INSTDONE register
3701 - intel/genxml: add GAM done register description
3702 - intel/hang_viewer: add aux-tt view
3729 - intel/ds: track predication of blorp operations
3751 - intel/aux_map: add BSpec reference
3752 - intel/aux_map: add helper to compute offset in aux data
3754 - intel/dev: fix missing dependency on generated packing heaers
3756 - intel/fs: indent lowering code to make it more readable
3757 - intel/fs: rerun divergence prior to lowering non-uniform interpolate at sample
3759 - meson: add a new option to enable intel-clc without building RT shaders
3760 - intel/compiler: make default NIR compiler options visible
3761 - intel-clc: move ISA generation to its own function
3762 - intel/clc: add ability to output NIR
3763 - intel-clc: print text input
3767 - intel/ds: new tracepoints for generated commands
3768 - meson: add option to install intel-clc
3771 - intel/shaders: add iris variant of indirect draws generation shader
3772 - intel/shaders: enable gfx8 support
3779 - meson: enforce build of intel-clc with anv/iris
3791 - intel/clc: lower temp function/shader variables together
3792 - intel/clc: workaround LLVM17 opaque pointers
3795 - intel/ci: bump anv/tgl fraction to 6
3796 - intel/nir: only consider ray query variables in lowering
3810 - intel/fs: add plumbing for embedded samplers
3830 - intel/fs: fixup sampler header message
3832 - intel/fs: remove some unused send helpers
3834 - intel/fs: bump max simd size of some messages for xe2
3853 - intel/fs: printout a couple of more late compile steps
3854 - intel/fs: fixup instruction scheduling last grf write tracking
3873 - intel/brw: fixup wm_prog_data_barycentric_modes()
3968 - intel/compiler/xe2: fix decoding of sampler simd mode
4256 - intel/dev: specify struct intel_device_info type details in python
4257 - intel/dev: generate declarations for struct intel_device_info
4258 - intel/tools: add intel device meson dependencies
4259 - intel/dev: implement json serialization for intel_device_info
4260 - intel/dev/tools: add json as an output format for intel_dev_info
4261 - intel/tools: load json device info in drm_shim
4262 - intel/dev: improve meson invocation for intel_device_info gen
4263 - intel/compiler: generate a hash function to use with the shader cache
4266 - intel/tools: move intel_dev_info to intel/tools
4267 - intel/tools: add shader compiler hash key to json devinfo format
4269 - intel/dev: declare workarounds required by ATSM platforms
4270 - intel/dev: remove pci revision from shader cache key
4271 - intel/compiler: drop unused ray-tracing fields from cache hash
4351 - intel: Build float64 shader only for Vulkan
4621 - intel: set compact_arrays in compiler options
4727 - intel/isl: Remove inconsistency when choosing Tile64
4728 - intel/isl: Remove inconsistency when encoding Tile64
4729 - intel/isl: Remove a CCS_D check from gfx12+ code
4730 - intel/isl: Enable a 64KB alignment WA for flat-CCS
4731 - intel/isl: Use Tile64 to align images for CCS WA
4732 - intel/isl: Disable miptails to align LODs for CCS WA
5054 - intel/compiler: Xe2+ can do URB load/store with a byte offset
5057 - intel/genxml: update PIPE_CONTROL so that we can decode it on the CCS
5059 - intel/brw: Use the dimensions supplied in the instruction
5060 - intel/brw: Cleanup send generation
5061 - intel/brw: Update written size depending on the LSC message
5062 - intel/brw: Set the right cache control bits for xe2
5063 - intel/brw: Adjust src1 length bits for xe2+
5067 - intel/brw: account for sources when determining if a operation uses half floats
5068 - intel/brw: Xe2+ can do SIMD16 for extended math on HF types
5069 - intel/brw: update disassembly for MATH pipe
5070 - intel/brw: adjust the copy propgation pass to account for wider GRF's on Xe2+
5071 - intel/brw: minor rework to de duplicate variable assignment
5072 - intel/brw: Handle typed surface and atomic messages for xe2+
5073 - intel/brw: Lower DWORD scattered read writes to lsc
5074 - intel/eu/validate: Allow SIMD16 for mixed mode float operations on xe2+
5076 - intel/blorp: add fast clear rectangle dimensions for single sampled TILE64 CCS surfaces
5110 - intel/fs: Track instance id in gs_thread_payload
5113 - intel/compiler/xe2: Handle 6-bit message type for Gfx20+
5114 - intel/compiler: Add texture operation lowering pass
5115 - intel/compiler: Use nir_tex_src_backend1 to pack LOD and array index
5116 - nir: Drop intel specific lowering code
5117 - intel/compiler: Lower texture operation to combine LOD and AI
5118 - intel/dev: Update max_subslices_per_slice comment
5119 - intel/compiler: Fix disassembly of URB message descriptor on Xe2+
5122 - intel/compiler: Trim vector properly till array index
5123 - intel/compiler: Adjust sample_b parameter according to new layout
5124 - intel/compiler: Pack LOD/bias and array index on TG4 messages
5125 - intel/compiler: Pack texture LOD and offset to a single 32-bit value
5126 - intel/compiler: Add helper method to decide if header is required
5127 - intel/compiler: Add gather4_i/l/[_c]/b sampler message
5128 - intel/compiler: Add texture gather offset LOD/Bias message support
5130 - intel/compiler: Enable packing of offset with LOD or Bias
5137 - intel/compiler: Disassemble mlen/rlen/ex_mlen in units of registers
5667 - intel/blorp: add a TODO note about stencil buffer resolve
5668 - intel: refactor urb configuration, add intel_urb_config
5669 - intel/common: provide a helper for urb setup comparison
5676 - intel/blorp: disable use of REP16 independent of format
5687 - intel/blorp: remove unused blorp batch flag
5688 - intel/compiler: add assert for Wa_22017182272
5952 - intel: Skip ioctls for querying device info when hardware is unsupported
6001 - intel/disasm: Remove duplicate variable reg_file
6002 - intel/clc: Fix file descriptor leak
6162 - intel/meson: Remove redundant inc_gallium