Lines Matching full:radeonsi

102 -  radeonsi: always set all blend registers
103 -  radeonsi: set CB_BLEND1_CONTROL.ENABLE for dual source blending
104 -  radeonsi: disable RB+ blend optimizations for dual source blending
105 -  radeonsi: consolidate max-work-group-size computation
106 -  radeonsi: apply a multi-wave workgroup SPI bug workaround to affected
108 -  radeonsi: apply a TC L1 write corruption workaround for SI
109 -  radeonsi: apply a tessellation bug workaround for SI
110 -  radeonsi: add a tess+GS hang workaround for VI dGPUs
111 -  radeonsi: apply the double EVENT_WRITE_EOP workaround to VI as well
113 -  radeonsi: always restore sampler states when unbinding sampler views
114 -  radeonsi: fix incorrect FMASK checking in bind_sampler_states
115 -  radeonsi: allow specifying simm16 of emit_waitcnt at call sites
116 -  radeonsi: wait for outstanding memory instructions in TCS barriers
118 -  radeonsi: wait for outstanding LDS instructions in memory barriers if
120 -  radeonsi: disable the constant engine (CE) on Carrizo and Stoney
134 -  radeonsi: fix isolines tess factor writes to control ring
135 -  radeonsi: update all GSVS ring descriptors for new buffer allocations
136 -  radeonsi: do not kill GS with memory writes
137 -  radeonsi: fix an off-by-one error in the bounds check for