Lines Matching full:old
13 %old = atomicrmw add i8* @var8, i8 %offset seq_cst
20 ; CHECK: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]]
23 ; CHECK-NEXT: add{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r0
30 ; CHECK: mov r0, r[[OLD]]
31 ret i8 %old
36 %old = atomicrmw add i16* @var16, i16 %offset acquire
43 ; CHECK: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]]
46 ; CHECK-NEXT: add{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r0
53 ; CHECK: mov r0, r[[OLD]]
54 ret i16 %old
59 %old = atomicrmw add i32* @var32, i32 %offset release
66 ; CHECK: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]]
69 ; CHECK-NEXT: add{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r0
76 ; CHECK: mov r0, r[[OLD]]
77 ret i32 %old
82 %old = atomicrmw add i64* @var64, i64 %offset monotonic
103 store i64 %old, i64* @var64
109 %old = atomicrmw sub i8* @var8, i8 %offset monotonic
116 ; CHECK: ldrexb r[[OLD:[0-9]+]], [r[[ADDR]]]
119 ; CHECK-NEXT: sub{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r0
126 ; CHECK: mov r0, r[[OLD]]
127 ret i8 %old
132 %old = atomicrmw sub i16* @var16, i16 %offset release
139 ; CHECK: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]]
142 ; CHECK-NEXT: sub{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r0
149 ; CHECK: mov r0, r[[OLD]]
150 ret i16 %old
155 %old = atomicrmw sub i32* @var32, i32 %offset acquire
162 ; CHECK: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]]
165 ; CHECK-NEXT: sub{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r0
172 ; CHECK: mov r0, r[[OLD]]
173 ret i32 %old
178 %old = atomicrmw sub i64* @var64, i64 %offset seq_cst
199 store i64 %old, i64* @var64
205 %old = atomicrmw and i8* @var8, i8 %offset release
212 ; CHECK: ldrexb r[[OLD:[0-9]+]], [r[[ADDR]]]
215 ; CHECK-NEXT: and{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0
222 ; CHECK: mov r0, r[[OLD]]
223 ret i8 %old
228 %old = atomicrmw and i16* @var16, i16 %offset monotonic
235 ; CHECK: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]]
238 ; CHECK-NEXT: and{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0
245 ; CHECK: mov r0, r[[OLD]]
246 ret i16 %old
251 %old = atomicrmw and i32* @var32, i32 %offset seq_cst
258 ; CHECK: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]]
261 ; CHECK-NEXT: and{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0
268 ; CHECK: mov r0, r[[OLD]]
269 ret i32 %old
274 %old = atomicrmw and i64* @var64, i64 %offset acquire
295 store i64 %old, i64* @var64
301 %old = atomicrmw or i8* @var8, i8 %offset seq_cst
308 ; CHECK: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]]
311 ; CHECK-NEXT: orr{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0
318 ; CHECK: mov r0, r[[OLD]]
319 ret i8 %old
324 %old = atomicrmw or i16* @var16, i16 %offset monotonic
331 ; CHECK: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]]
334 ; CHECK-NEXT: orr{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0
341 ; CHECK: mov r0, r[[OLD]]
342 ret i16 %old
347 %old = atomicrmw or i32* @var32, i32 %offset acquire
354 ; CHECK: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]]
357 ; CHECK-NEXT: orr{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0
364 ; CHECK: mov r0, r[[OLD]]
365 ret i32 %old
370 %old = atomicrmw or i64* @var64, i64 %offset release
391 store i64 %old, i64* @var64
397 %old = atomicrmw xor i8* @var8, i8 %offset acquire
404 ; CHECK: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]]
407 ; CHECK-NEXT: eor{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0
414 ; CHECK: mov r0, r[[OLD]]
415 ret i8 %old
420 %old = atomicrmw xor i16* @var16, i16 %offset release
427 ; CHECK: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]]
430 ; CHECK-NEXT: eor{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0
437 ; CHECK: mov r0, r[[OLD]]
438 ret i16 %old
443 %old = atomicrmw xor i32* @var32, i32 %offset seq_cst
450 ; CHECK: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]]
453 ; CHECK-NEXT: eor{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0
460 ; CHECK: mov r0, r[[OLD]]
461 ret i32 %old
466 %old = atomicrmw xor i64* @var64, i64 %offset monotonic
487 store i64 %old, i64* @var64
493 %old = atomicrmw xchg i8* @var8, i8 %offset monotonic
500 ; CHECK: ldrexb r[[OLD:[0-9]+]], [r[[ADDR]]]
509 ; CHECK: mov r0, r[[OLD]]
510 ret i8 %old
515 %old = atomicrmw xchg i16* @var16, i16 %offset seq_cst
522 ; CHECK: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]]
531 ; CHECK: mov r0, r[[OLD]]
532 ret i16 %old
537 %old = atomicrmw xchg i32* @var32, i32 %offset release
544 ; CHECK: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]]
553 ; CHECK: mov r0, r[[OLD]]
554 ret i32 %old
559 %old = atomicrmw xchg i64* @var64, i64 %offset acquire
576 store i64 %old, i64* @var64
582 %old = atomicrmw min i8* @var8, i8 %offset acquire
589 ; CHECK: ldaexb r[[OLD:[0-9]+]], {{.*}}[[ADDR]]
590 ; CHECK-NEXT: sxtb r[[OLDX:[0-9]+]], r[[OLD]]
595 ; CHECK: movle r[[OLDX]], r[[OLD]]
602 ; CHECK: mov r0, r[[OLD]]
603 ret i8 %old
608 %old = atomicrmw min i16* @var16, i16 %offset release
615 ; CHECK: ldrexh r[[OLD:[0-9]+]], {{.*}}[[ADDR]]
616 ; CHECK-NEXT: sxth r[[OLDX:[0-9]+]], r[[OLD]]
621 ; CHECK: movle r[[OLDX]], r[[OLD]]
628 ; CHECK: mov r0, r[[OLD]]
629 ret i16 %old
634 %old = atomicrmw min i32* @var32, i32 %offset monotonic
641 ; CHECK: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]]
645 ; CHECK-NEXT: cmp r[[OLD]], r0
647 ; CHECK: movle r[[NEW]], r[[OLD]]
654 ; CHECK: mov r0, r[[OLD]]
655 ret i32 %old
660 %old = atomicrmw min i64* @var64, i64 %offset seq_cst
689 store i64 %old, i64* @var64
695 %old = atomicrmw max i8* @var8, i8 %offset seq_cst
702 ; CHECK: ldaexb r[[OLD:[0-9]+]], {{.*}}[[ADDR]]
703 ; CHECK-NEXT: sxtb r[[OLDX:[0-9]+]], r[[OLD]]
708 ; CHECK: movgt r[[OLDX]], r[[OLD]]
715 ; CHECK: mov r0, r[[OLD]]
716 ret i8 %old
721 %old = atomicrmw max i16* @var16, i16 %offset acquire
728 ; CHECK: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]]
729 ; CHECK-NEXT: sxth r[[OLDX:[0-9]+]], r[[OLD]]
734 ; CHECK: movgt r[[OLDX]], r[[OLD]]
741 ; CHECK: mov r0, r[[OLD]]
742 ret i16 %old
747 %old = atomicrmw max i32* @var32, i32 %offset release
754 ; CHECK: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]]
758 ; CHECK-NEXT: cmp r[[OLD]], r0
760 ; CHECK: movgt r[[NEW]], r[[OLD]]
767 ; CHECK: mov r0, r[[OLD]]
768 ret i32 %old
773 %old = atomicrmw max i64* @var64, i64 %offset monotonic
802 store i64 %old, i64* @var64
808 %old = atomicrmw umin i8* @var8, i8 %offset monotonic
815 ; CHECK: ldrexb r[[OLD:[0-9]+]], {{.*}}[[ADDR]]
819 ; CHECK-NEXT: cmp r[[OLD]], r0
821 ; CHECK: movls r[[NEW]], r[[OLD]]
828 ; CHECK: mov r0, r[[OLD]]
829 ret i8 %old
834 %old = atomicrmw umin i16* @var16, i16 %offset acquire
841 ; CHECK: ldaexh r[[OLD:[0-9]+]], {{.*}}[[ADDR]]
845 ; CHECK-NEXT: cmp r[[OLD]], r0
847 ; CHECK: movls r[[NEW]], r[[OLD]]
854 ; CHECK: mov r0, r[[OLD]]
855 ret i16 %old
860 %old = atomicrmw umin i32* @var32, i32 %offset seq_cst
867 ; CHECK: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]]
871 ; CHECK-NEXT: cmp r[[OLD]], r0
873 ; CHECK: movls r[[NEW]], r[[OLD]]
880 ; CHECK: mov r0, r[[OLD]]
881 ret i32 %old
886 %old = atomicrmw umin i64* @var64, i64 %offset seq_cst
915 store i64 %old, i64* @var64
921 %old = atomicrmw umax i8* @var8, i8 %offset acq_rel
928 ; CHECK: ldaexb r[[OLD:[0-9]+]], {{.*}}[[ADDR]]
932 ; CHECK-NEXT: cmp r[[OLD]], r0
934 ; CHECK: movhi r[[NEW]], r[[OLD]]
941 ; CHECK: mov r0, r[[OLD]]
942 ret i8 %old
947 %old = atomicrmw umax i16* @var16, i16 %offset monotonic
954 ; CHECK: ldrexh r[[OLD:[0-9]+]], {{.*}}[[ADDR]]
958 ; CHECK-NEXT: cmp r[[OLD]], r0
960 ; CHECK: movhi r[[NEW]], r[[OLD]]
967 ; CHECK: mov r0, r[[OLD]]
968 ret i16 %old
973 %old = atomicrmw umax i32* @var32, i32 %offset seq_cst
980 ; CHECK: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]]
984 ; CHECK-NEXT: cmp r[[OLD]], r0
986 ; CHECK: movhi r[[NEW]], r[[OLD]]
993 ; CHECK: mov r0, r[[OLD]]
994 ret i32 %old
999 %old = atomicrmw umax i64* @var64, i64 %offset seq_cst
1028 store i64 %old, i64* @var64
1035 %old = extractvalue { i8, i1 } %pair, 0
1043 ; CHECK: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]]
1046 ; CHECK-ARM-NEXT: cmp r[[OLD]], r0
1047 ; CHECK-THUMB-NEXT: cmp r[[OLD]], r[[WANTED]]
1061 ; CHECK-ARM: mov r0, r[[OLD]]
1062 ret i8 %old
1068 %old = extractvalue { i16, i1 } %pair, 0
1076 ; CHECK: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]]
1079 ; CHECK-ARM-NEXT: cmp r[[OLD]], r0
1080 ; CHECK-THUMB-NEXT: cmp r[[OLD]], r[[WANTED]]
1094 ; CHECK-ARM: mov r0, r[[OLD]]
1095 ret i16 %old
1101 %old = extractvalue { i32, i1 } %pair, 0
1102 store i32 %old, i32* @var32
1109 ; CHECK: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]]
1112 ; CHECK-NEXT: cmp r[[OLD]], r0
1126 ; CHECK: str{{(.w)?}} r[[OLD]],
1133 %old = extractvalue { i64, i1 } %pair, 0
1165 store i64 %old, i64* @var64