Lines Matching +full:60 +full:s
144 def XSADDDP : XX3Form<60, 32,
148 def XSMULDP : XX3Form<60, 48,
153 def XVADDDP : XX3Form<60, 96,
158 def XVADDSP : XX3Form<60, 64,
163 def XVMULDP : XX3Form<60, 112,
168 def XVMULSP : XX3Form<60, 80,
175 def XSSUBDP : XX3Form<60, 40,
180 def XVSUBDP : XX3Form<60, 104,
184 def XVSUBSP : XX3Form<60, 72,
192 def XSMADDADP : XX3Form<60, 33,
199 def XSMADDMDP : XX3Form<60, 41,
208 def XSMSUBADP : XX3Form<60, 49,
215 def XSMSUBMDP : XX3Form<60, 57,
224 def XSNMADDADP : XX3Form<60, 161,
231 def XSNMADDMDP : XX3Form<60, 169,
240 def XSNMSUBADP : XX3Form<60, 177,
247 def XSNMSUBMDP : XX3Form<60, 185,
256 def XVMADDADP : XX3Form<60, 97,
263 def XVMADDMDP : XX3Form<60, 105,
272 def XVMADDASP : XX3Form<60, 65,
279 def XVMADDMSP : XX3Form<60, 73,
288 def XVMSUBADP : XX3Form<60, 113,
295 def XVMSUBMDP : XX3Form<60, 121,
304 def XVMSUBASP : XX3Form<60, 81,
311 def XVMSUBMSP : XX3Form<60, 89,
320 def XVNMADDADP : XX3Form<60, 225,
327 def XVNMADDMDP : XX3Form<60, 233,
336 def XVNMADDASP : XX3Form<60, 193,
343 def XVNMADDMSP : XX3Form<60, 201,
352 def XVNMSUBADP : XX3Form<60, 241,
359 def XVNMSUBMDP : XX3Form<60, 249,
368 def XVNMSUBASP : XX3Form<60, 209,
375 def XVNMSUBMSP : XX3Form<60, 217,
383 def XSDIVDP : XX3Form<60, 56,
387 def XSSQRTDP : XX2Form<60, 75,
392 def XSREDP : XX2Form<60, 90,
396 def XSRSQRTEDP : XX2Form<60, 74,
401 def XSTDIVDP : XX3Form_1<60, 61,
404 def XSTSQRTDP : XX2Form_1<60, 106,
408 def XVDIVDP : XX3Form<60, 120,
412 def XVDIVSP : XX3Form<60, 88,
417 def XVSQRTDP : XX2Form<60, 203,
421 def XVSQRTSP : XX2Form<60, 139,
426 def XVTDIVDP : XX3Form_1<60, 125,
429 def XVTDIVSP : XX3Form_1<60, 93,
433 def XVTSQRTDP : XX2Form_1<60, 234,
436 def XVTSQRTSP : XX2Form_1<60, 170,
440 def XVREDP : XX2Form<60, 218,
444 def XVRESP : XX2Form<60, 154,
449 def XVRSQRTEDP : XX2Form<60, 202,
453 def XVRSQRTESP : XX2Form<60, 138,
459 def XSCMPODP : XX3Form_1<60, 43,
462 def XSCMPUDP : XX3Form_1<60, 35,
466 defm XVCMPEQDP : XX3Form_Rcr<60, 99,
469 defm XVCMPEQSP : XX3Form_Rcr<60, 67,
472 defm XVCMPGEDP : XX3Form_Rcr<60, 115,
475 defm XVCMPGESP : XX3Form_Rcr<60, 83,
478 defm XVCMPGTDP : XX3Form_Rcr<60, 107,
481 defm XVCMPGTSP : XX3Form_Rcr<60, 75,
486 def XSABSDP : XX2Form<60, 345,
490 def XSNABSDP : XX2Form<60, 361,
494 def XSNEGDP : XX2Form<60, 377,
498 def XSCPSGNDP : XX3Form<60, 176,
503 def XVABSDP : XX2Form<60, 473,
508 def XVABSSP : XX2Form<60, 409,
513 def XVCPSGNDP : XX3Form<60, 240,
517 def XVCPSGNSP : XX3Form<60, 208,
522 def XVNABSDP : XX2Form<60, 489,
526 def XVNABSSP : XX2Form<60, 425,
531 def XVNEGDP : XX2Form<60, 505,
535 def XVNEGSP : XX2Form<60, 441,
541 def XSCVDPSP : XX2Form<60, 265,
544 def XSCVDPSXDS : XX2Form<60, 344,
548 def XSCVDPSXWS : XX2Form<60, 88,
552 def XSCVDPUXDS : XX2Form<60, 328,
556 def XSCVDPUXWS : XX2Form<60, 72,
560 def XSCVSPDP : XX2Form<60, 329,
563 def XSCVSXDDP : XX2Form<60, 376,
567 def XSCVUXDDP : XX2Form<60, 360,
572 def XVCVDPSP : XX2Form<60, 393,
575 def XVCVDPSXDS : XX2Form<60, 472,
579 def XVCVDPSXWS : XX2Form<60, 216,
582 def XVCVDPUXDS : XX2Form<60, 456,
586 def XVCVDPUXWS : XX2Form<60, 200,
590 def XVCVSPDP : XX2Form<60, 457,
593 def XVCVSPSXDS : XX2Form<60, 408,
596 def XVCVSPSXWS : XX2Form<60, 152,
599 def XVCVSPUXDS : XX2Form<60, 392,
602 def XVCVSPUXWS : XX2Form<60, 136,
605 def XVCVSXDDP : XX2Form<60, 504,
609 def XVCVSXDSP : XX2Form<60, 440,
612 def XVCVSXWDP : XX2Form<60, 248,
615 def XVCVSXWSP : XX2Form<60, 184,
619 def XVCVUXDDP : XX2Form<60, 488,
623 def XVCVUXDSP : XX2Form<60, 424,
626 def XVCVUXWDP : XX2Form<60, 232,
629 def XVCVUXWSP : XX2Form<60, 168,
634 def XSRDPI : XX2Form<60, 73,
638 def XSRDPIC : XX2Form<60, 107,
642 def XSRDPIM : XX2Form<60, 121,
646 def XSRDPIP : XX2Form<60, 105,
650 def XSRDPIZ : XX2Form<60, 89,
655 def XVRDPI : XX2Form<60, 201,
659 def XVRDPIC : XX2Form<60, 235,
663 def XVRDPIM : XX2Form<60, 249,
667 def XVRDPIP : XX2Form<60, 233,
671 def XVRDPIZ : XX2Form<60, 217,
676 def XVRSPI : XX2Form<60, 137,
680 def XVRSPIC : XX2Form<60, 171,
684 def XVRSPIM : XX2Form<60, 185,
688 def XVRSPIP : XX2Form<60, 169,
692 def XVRSPIZ : XX2Form<60, 153,
699 def XSMAXDP : XX3Form<60, 160,
704 def XSMINDP : XX3Form<60, 168,
710 def XVMAXDP : XX3Form<60, 224,
715 def XVMINDP : XX3Form<60, 232,
721 def XVMAXSP : XX3Form<60, 192,
726 def XVMINSP : XX3Form<60, 200,
736 def XXLAND : XX3Form<60, 130,
740 def XXLANDC : XX3Form<60, 138,
746 def XXLNOR : XX3Form<60, 162,
751 def XXLOR : XX3Form<60, 146,
756 def XXLORf: XX3Form<60, 146,
759 def XXLXOR : XX3Form<60, 154,
766 def XXMRGHW : XX3Form<60, 18,
769 def XXMRGLW : XX3Form<60, 50,
773 def XXPERMDI : XX3Form_2<60, 10,
776 def XXSEL : XX4Form<60, 3,
780 def XXSLDWI : XX3Form_2<60, 2,
785 def XXSPLTW : XX2Form_2<60, 164,
849 def : Pat<(f64 (extractelt v2f64:$S, 0)),
850 (f64 (EXTRACT_SUBREG $S, sub_64))>;
851 def : Pat<(f64 (extractelt v2f64:$S, 1)),
852 (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;
860 def : Pat<(f64 (extractelt v2f64:$S, 0)),
861 (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;
862 def : Pat<(f64 (extractelt v2f64:$S, 1)),
863 (f64 (EXTRACT_SUBREG $S, sub_64))>;
1045 def XXLEQV : XX3Form<60, 186,
1049 def XXLNAND : XX3Form<60, 178,
1059 def XXLORC : XX3Form<60, 170,
1115 def XSADDSP : XX3Form<60, 0,
1119 def XSMULSP : XX3Form<60, 16,
1125 def XSDIVSP : XX3Form<60, 24,
1129 def XSRESP : XX2Form<60, 26,
1133 def XSSQRTSP : XX2Form<60, 11,
1137 def XSRSQRTESP : XX2Form<60, 10,
1141 def XSSUBSP : XX3Form<60, 8,
1149 def XSMADDASP : XX3Form<60, 1,
1157 def XSMADDMSP : XX3Form<60, 9,
1167 def XSMSUBASP : XX3Form<60, 17,
1176 def XSMSUBMSP : XX3Form<60, 25,
1186 def XSNMADDASP : XX3Form<60, 129,
1195 def XSNMADDMSP : XX3Form<60, 137,
1205 def XSNMSUBASP : XX3Form<60, 145,
1214 def XSNMSUBMSP : XX3Form<60, 153,
1223 def XSCVSXDSP : XX2Form<60, 312,
1227 def XSCVUXDSP : XX2Form<60, 296,
1233 def XSCVDPSPN : XX2Form<60, 267, (outs vsrc:$XT), (ins vssrc:$XB),
1235 def XSCVSPDPN : XX2Form<60, 331, (outs vssrc:$XT), (ins vsrc:$XB),
1277 /* Direct moves of various widths from GPR's into VSR's. Each move lines
1310 The numbering for the DAG's is for LE, but when used on BE, the correct
1318 (XXPERMDI (COPY_TO_REGCLASS $S, VSRC),
1319 (COPY_TO_REGCLASS $S, VSRC), 2), sub_64));
1322 (v2i64 (COPY_TO_REGCLASS $S, VSRC)), sub_64));
1325 dag LE_WORD_0 = (MFVSRWZ (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64));
1326 dag LE_WORD_1 = (MFVSRWZ (EXTRACT_SUBREG (XXSLDWI $S, $S, 1), sub_64));
1328 (v2i64 (COPY_TO_REGCLASS $S, VSRC)), sub_64));
1329 dag LE_WORD_3 = (MFVSRWZ (EXTRACT_SUBREG (XXSLDWI $S, $S, 3), sub_64));
1383 with 0x8 (i.e. clearing all bits of the index and inverting bit 60).
1389 dag LE_VBYTE_PERMUTE = (VPERM $S, $S, LE_VBYTE_PERM_VEC);
1404 dag LE_VBYTE_SHIFT = (EXTRACT_SUBREG (RLDICR (AND8 (LI8 7), $Idx), 3, 60),
1421 dag LE_VHALF_PERMUTE = (VPERM $S, $S, LE_VHALF_PERM_VEC);
1450 dag LE_VWORD_PERMUTE = (VPERM $S, $S, LE_VWORD_PERM_VEC);
1472 - For element 0, we shift left by 8 since it's on the right
1475 dag LE_VDWORD_PERM_VEC = (LVSL ZERO8, (RLDICR (ANDC8 (LI8 1), $Idx), 3, 60));
1479 dag LE_VDWORD_PERMUTE = (VPERM $S, $S, LE_VDWORD_PERM_VEC);
1494 dag LE_VFLOAT_PERMUTE = (VPERM $S, $S, LE_VFLOAT_PERM_VEC);
1500 dag LE_VDOUBLE_PERMUTE = (VPERM (COPY_TO_REGCLASS $S, VRRC),
1501 (COPY_TO_REGCLASS $S, VRRC),
1513 dag BE_VBYTE_PERMUTE = (VPERM $S, $S, BE_VBYTE_PERM_VEC);
1518 dag BE_VBYTE_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 7), $Idx), 3, 60),
1531 dag BE_VHALF_PERMUTE = (VPERM $S, $S, BE_VHALF_PERM_VEC);
1548 dag BE_VWORD_PERMUTE = (VPERM $S, $S, BE_VWORD_PERM_VEC);
1562 dag BE_VDWORD_PERM_VEC = (LVSL ZERO8, (RLDICR (ANDIo8 $Idx, 1), 3, 60));
1563 dag BE_VDWORD_PERMUTE = (VPERM $S, $S, BE_VDWORD_PERM_VEC);
1574 dag BE_VFLOAT_PERMUTE = (VPERM $S, $S, BE_VFLOAT_PERM_VEC);
1580 dag BE_VDOUBLE_PERMUTE = (VPERM (COPY_TO_REGCLASS $S, VRRC),
1581 (COPY_TO_REGCLASS $S, VRRC),
1590 def : Pat<(f32 (vector_extract v4f32:$S, 0)),
1591 (f32 (XSCVSPDPN $S))>;
1592 def : Pat<(f32 (vector_extract v4f32:$S, 1)),
1593 (f32 (XSCVSPDPN (XXSLDWI $S, $S, 1)))>;
1594 def : Pat<(f32 (vector_extract v4f32:$S, 2)),
1595 (f32 (XSCVSPDPN (XXPERMDI $S, $S, 2)))>;
1596 def : Pat<(f32 (vector_extract v4f32:$S, 3)),
1597 (f32 (XSCVSPDPN (XXSLDWI $S, $S, 3)))>;
1598 def : Pat<(f32 (vector_extract v4f32:$S, i64:$Idx)),
1604 def : Pat<(f64 (vector_extract v2f64:$S, i64:$Idx)),
1617 def : Pat<(i32 (vector_extract v16i8:$S, 0)),
1619 def : Pat<(i32 (vector_extract v16i8:$S, 1)),
1621 def : Pat<(i32 (vector_extract v16i8:$S, 2)),
1623 def : Pat<(i32 (vector_extract v16i8:$S, 3)),
1625 def : Pat<(i32 (vector_extract v16i8:$S, 4)),
1627 def : Pat<(i32 (vector_extract v16i8:$S, 5)),
1629 def : Pat<(i32 (vector_extract v16i8:$S, 6)),
1631 def : Pat<(i32 (vector_extract v16i8:$S, 7)),
1633 def : Pat<(i32 (vector_extract v16i8:$S, 8)),
1635 def : Pat<(i32 (vector_extract v16i8:$S, 9)),
1637 def : Pat<(i32 (vector_extract v16i8:$S, 10)),
1639 def : Pat<(i32 (vector_extract v16i8:$S, 11)),
1641 def : Pat<(i32 (vector_extract v16i8:$S, 12)),
1643 def : Pat<(i32 (vector_extract v16i8:$S, 13)),
1645 def : Pat<(i32 (vector_extract v16i8:$S, 14)),
1647 def : Pat<(i32 (vector_extract v16i8:$S, 15)),
1649 def : Pat<(i32 (vector_extract v16i8:$S, i64:$Idx)),
1653 def : Pat<(i32 (vector_extract v8i16:$S, 0)),
1655 def : Pat<(i32 (vector_extract v8i16:$S, 1)),
1657 def : Pat<(i32 (vector_extract v8i16:$S, 2)),
1659 def : Pat<(i32 (vector_extract v8i16:$S, 3)),
1661 def : Pat<(i32 (vector_extract v8i16:$S, 4)),
1663 def : Pat<(i32 (vector_extract v8i16:$S, 5)),
1665 def : Pat<(i32 (vector_extract v8i16:$S, 6)),
1667 def : Pat<(i32 (vector_extract v8i16:$S, 7)),
1669 def : Pat<(i32 (vector_extract v8i16:$S, i64:$Idx)),
1673 def : Pat<(i32 (vector_extract v4i32:$S, 0)),
1675 def : Pat<(i32 (vector_extract v4i32:$S, 1)),
1677 def : Pat<(i32 (vector_extract v4i32:$S, 2)),
1679 def : Pat<(i32 (vector_extract v4i32:$S, 3)),
1681 def : Pat<(i32 (vector_extract v4i32:$S, i64:$Idx)),
1685 def : Pat<(i64 (vector_extract v2i64:$S, 0)),
1687 def : Pat<(i64 (vector_extract v2i64:$S, 1)),
1689 def : Pat<(i64 (vector_extract v2i64:$S, i64:$Idx)),
1697 def : Pat<(f32 (vector_extract v4f32:$S, 0)),
1698 (f32 (XSCVSPDPN (XXSLDWI $S, $S, 3)))>;
1699 def : Pat<(f32 (vector_extract v4f32:$S, 1)),
1700 (f32 (XSCVSPDPN (XXPERMDI $S, $S, 2)))>;
1701 def : Pat<(f32 (vector_extract v4f32:$S, 2)),
1702 (f32 (XSCVSPDPN (XXSLDWI $S, $S, 1)))>;
1703 def : Pat<(f32 (vector_extract v4f32:$S, 3)),
1704 (f32 (XSCVSPDPN $S))>;
1705 def : Pat<(f32 (vector_extract v4f32:$S, i64:$Idx)),
1711 def : Pat<(f64 (vector_extract v2f64:$S, i64:$Idx)),
1724 def : Pat<(i32 (vector_extract v16i8:$S, 0)),
1726 def : Pat<(i32 (vector_extract v16i8:$S, 1)),
1728 def : Pat<(i32 (vector_extract v16i8:$S, 2)),
1730 def : Pat<(i32 (vector_extract v16i8:$S, 3)),
1732 def : Pat<(i32 (vector_extract v16i8:$S, 4)),
1734 def : Pat<(i32 (vector_extract v16i8:$S, 5)),
1736 def : Pat<(i32 (vector_extract v16i8:$S, 6)),
1738 def : Pat<(i32 (vector_extract v16i8:$S, 7)),
1740 def : Pat<(i32 (vector_extract v16i8:$S, 8)),
1742 def : Pat<(i32 (vector_extract v16i8:$S, 9)),
1744 def : Pat<(i32 (vector_extract v16i8:$S, 10)),
1746 def : Pat<(i32 (vector_extract v16i8:$S, 11)),
1748 def : Pat<(i32 (vector_extract v16i8:$S, 12)),
1750 def : Pat<(i32 (vector_extract v16i8:$S, 13)),
1752 def : Pat<(i32 (vector_extract v16i8:$S, 14)),
1754 def : Pat<(i32 (vector_extract v16i8:$S, 15)),
1756 def : Pat<(i32 (vector_extract v16i8:$S, i64:$Idx)),
1760 def : Pat<(i32 (vector_extract v8i16:$S, 0)),
1762 def : Pat<(i32 (vector_extract v8i16:$S, 1)),
1764 def : Pat<(i32 (vector_extract v8i16:$S, 2)),
1766 def : Pat<(i32 (vector_extract v8i16:$S, 3)),
1768 def : Pat<(i32 (vector_extract v8i16:$S, 4)),
1770 def : Pat<(i32 (vector_extract v8i16:$S, 5)),
1772 def : Pat<(i32 (vector_extract v8i16:$S, 6)),
1774 def : Pat<(i32 (vector_extract v8i16:$S, 7)),
1776 def : Pat<(i32 (vector_extract v8i16:$S, i64:$Idx)),
1780 def : Pat<(i32 (vector_extract v4i32:$S, 0)),
1782 def : Pat<(i32 (vector_extract v4i32:$S, 1)),
1784 def : Pat<(i32 (vector_extract v4i32:$S, 2)),
1786 def : Pat<(i32 (vector_extract v4i32:$S, 3)),
1788 def : Pat<(i32 (vector_extract v4i32:$S, i64:$Idx)),
1792 def : Pat<(i64 (vector_extract v2i64:$S, 0)),
1794 def : Pat<(i64 (vector_extract v2i64:$S, 1)),
1796 def : Pat<(i64 (vector_extract v2i64:$S, i64:$Idx)),
1803 def : Pat<(i32 (bitconvert f32:$S)),
1805 (XXSLDWI (XSCVDPSPN $S),(XSCVDPSPN $S), 3),
1815 def : Pat<(i64 (bitconvert f64:$S)),
1816 (i64 (MFVSRD $S))>;
1820 def : Pat<(f64 (bitconvert i64:$S)),
1821 (f64 (MTVSRD $S))>;
1935 def XSCMPEXPDP : XX3Form_1<60, 59,
1943 def XSCMPEQDP : XX3_XT5_XA5_XB5<60, 3, "xscmpeqdp", vsrc, vsfrc, vsfrc,
1945 def XSCMPGEDP : XX3_XT5_XA5_XB5<60, 19, "xscmpgedp", vsrc, vsfrc, vsfrc,
1947 def XSCMPGTDP : XX3_XT5_XA5_XB5<60, 11, "xscmpgtdp", vsrc, vsfrc, vsfrc,
1949 def XSCMPNEDP : XX3_XT5_XA5_XB5<60, 27, "xscmpnedp", vsrc, vsfrc, vsfrc,
1952 def XVCMPNEDP : XX3Form_Rc<60, 123,
1956 def XVCMPNEDPo : XX3Form_Rc<60, 123,
1960 def XVCMPNESP : XX3Form_Rc<60, 91,
1964 def XVCMPNESPo : XX3Form_Rc<60, 91,
1993 // Note! xscvdphp's src and dest register both use the left 64 bits, so we use
1994 // vsfrc for src and dest register. xscvhpdp's src only use the left 16 bits,
1996 def XSCVDPHP : XX2_XT6_XO5_XB6<60, 17, 347, "xscvdphp", vsfrc, []>;
1997 def XSCVHPDP : XX2_XT6_XO5_XB6<60, 16, 347, "xscvhpdp", vsfrc, []>;
2000 def XVCVHPSP : XX2_XT6_XO5_XB6<60, 24, 475, "xvcvhpsp", vsrc, []>;
2001 def XVCVSPHP : XX2_XT6_XO5_XB6<60, 25, 475, "xvcvsphp", vsrc, []>;
2023 def XSIEXPDP : XX1Form <60, 918, (outs vsrc:$XT), (ins g8rc:$rA, g8rc:$rB),
2025 // vB NOTE: only vB.dword[0] is used, that's why we don't use
2031 def XSXEXPDP : XX2_RT5_XO5_XB6<60, 0, 347, "xsxexpdp", []>;
2032 def XSXSIGDP : XX2_RT5_XO5_XB6<60, 1, 347, "xsxsigdp", []>;
2039 XX2_RD6_UIM5_RS6<60, 181, (outs vsrc:$XT),
2047 def XXEXTRACTUW : XX2_RD6_UIM5_RS6<60, 165,
2052 def XVIEXPDP : XX3_XT5_XA5_XB5<60, 248, "xviexpdp", vsrc, vsrc, vsrc,
2054 def XVIEXPSP : XX3_XT5_XA5_XB5<60, 216, "xviexpsp", vsrc, vsrc, vsrc,
2058 def XVXEXPDP : XX2_XT6_XO5_XB6<60, 0, 475, "xvxexpdp", vsrc, []>;
2059 def XVXEXPSP : XX2_XT6_XO5_XB6<60, 8, 475, "xvxexpsp", vsrc, []>;
2060 def XVXSIGDP : XX2_XT6_XO5_XB6<60, 1, 475, "xvxsigdp", vsrc, []>;
2061 def XVXSIGSP : XX2_XT6_XO5_XB6<60, 9, 475, "xvxsigsp", vsrc, []>;
2066 def XSTSTDCSP : XX2_BF3_DCMX7_RS6<60, 298,
2069 def XSTSTDCDP : XX2_BF3_DCMX7_RS6<60, 362,
2077 def XVTSTDCSP : XX2_RD6_DCMX7_RS6<60, 13, 5,
2080 def XVTSTDCDP : XX2_RD6_DCMX7_RS6<60, 15, 5,
2088 def XSMAXCDP : XX3_XT5_XA5_XB5<60, 128, "xsmaxcdp", vsrc, vsfrc, vsfrc,
2090 def XSMAXJDP : XX3_XT5_XA5_XB5<60, 144, "xsmaxjdp", vsrc, vsfrc, vsfrc,
2092 def XSMINCDP : XX3_XT5_XA5_XB5<60, 136, "xsmincdp", vsrc, vsfrc, vsfrc,
2094 def XSMINJDP : XX3_XT5_XA5_XB5<60, 152, "xsminjdp", vsrc, vsfrc, vsfrc,
2100 def XXBRH : XX2_XT6_XO5_XB6<60, 7, 475, "xxbrh", vsrc, []>;
2101 def XXBRW : XX2_XT6_XO5_XB6<60, 15, 475, "xxbrw", vsrc, []>;
2102 def XXBRD : XX2_XT6_XO5_XB6<60, 23, 475, "xxbrd", vsrc, []>;
2103 def XXBRQ : XX2_XT6_XO5_XB6<60, 31, 475, "xxbrq", vsrc, []>;
2106 def XXPERM : XX3_XT5_XA5_XB5<60, 26, "xxperm" , vsrc, vsrc, vsrc,
2108 def XXPERMR : XX3_XT5_XA5_XB5<60, 58, "xxpermr", vsrc, vsrc, vsrc,
2112 def XXSPLTIB : X_RD6_IMM8<60, 360, (outs vsrc:$XT), (ins u8imm:$IMM8),
2129 // [PO T RA RB XO TX] almost equal to [PO S RA RB XO SX], but has different
2166 // [PO S RA RB XO SX]