Lines Matching full:supports
69 * CPU supports the VFPv2 instruction set. Many, but not all, ARMv6 CPUs
74 * CPU supports the ARMv7-A basic instruction set.
78 * CPU supports the VFPv3-D16 instruction set, providing hardware FPU
90 * CPU FPU supports "ARM Advanced SIMD" instructions, also known as
96 * supports instructions to perform floating-point operations on
123 * CPU supports AES instructions. These instructions are only
127 * CPU supports CRC32 instructions. These instructions are only
131 * CPU supports SHA2 instructions. These instructions are only
135 * CPU supports SHA1 instructions. These instructions are only
139 * CPU supports 64-bit PMULL and PMULL2 instructions. These
158 * This should be generic code that runs on any CPU that supports the
159 * 'armeabi-v7a' Android ABI. Note that no ARMv6 CPU supports this.
229 * CPU supports AES instructions.
232 * CPU supports CRC32 instructions.
235 * CPU supports SHA2 instructions.
238 * CPU supports SHA1 instructions.
241 * CPU supports 64-bit PMULL and PMULL2 instructions.
276 * supports obsoleted R1..R5 instructions only via kernel traps.
279 * CPU supports Mips SIMD Architecture instructions.
287 * Please note the current implementation supports up to 32 cpus.