Lines Matching full:mask
116 uint32_t reg, mask, field; in mvebu_cp110_comphy_clr_pipe_selector() local
120 mask = COMMON_SELECTOR_COMPHY_MASK << comphy_offset; in mvebu_cp110_comphy_clr_pipe_selector()
122 field = reg & mask; in mvebu_cp110_comphy_clr_pipe_selector()
125 reg &= ~mask; in mvebu_cp110_comphy_clr_pipe_selector()
135 uint32_t reg, mask, field; in mvebu_cp110_comphy_clr_phy_selector() local
139 mask = COMMON_SELECTOR_COMPHY_MASK << comphy_offset; in mvebu_cp110_comphy_clr_phy_selector()
141 field = reg & mask; in mvebu_cp110_comphy_clr_phy_selector()
149 reg &= ~mask; in mvebu_cp110_comphy_clr_phy_selector()
159 uint32_t reg, mask; in mvebu_cp110_comphy_set_phy_selector() local
174 mask = COMMON_SELECTOR_COMPHY_MASK << comphy_offset; in mvebu_cp110_comphy_set_phy_selector()
176 reg &= ~mask; in mvebu_cp110_comphy_set_phy_selector()
256 uint32_t mask = COMMON_SELECTOR_COMPHY_MASK << shift; in mvebu_cp110_comphy_set_pipe_selector() local
265 reg &= ~mask; in mvebu_cp110_comphy_set_pipe_selector()
305 uint32_t mask, data; in mvebu_cp110_comphy_is_pll_locked() local
316 mask = data; in mvebu_cp110_comphy_is_pll_locked()
317 data = polling_with_timeout(addr, data, mask, in mvebu_cp110_comphy_is_pll_locked()
335 uint32_t mask, data; in mvebu_cp110_polarity_invert() local
338 data = mask = 0x0U; in mvebu_cp110_polarity_invert()
341 mask |= HPIPE_SYNC_PATTERN_TXD_INV_MASK; in mvebu_cp110_polarity_invert()
347 mask |= HPIPE_SYNC_PATTERN_RXD_INV_MASK; in mvebu_cp110_polarity_invert()
351 reg_set(addr, data, mask); in mvebu_cp110_polarity_invert()
358 uint32_t mask, data; in mvebu_cp110_comphy_sata_power_on() local
385 mask = COMMON_PHY_CFG1_PWR_UP_MASK; in mvebu_cp110_comphy_sata_power_on()
387 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; in mvebu_cp110_comphy_sata_power_on()
389 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; in mvebu_cp110_comphy_sata_power_on()
391 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; in mvebu_cp110_comphy_sata_power_on()
393 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
401 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in mvebu_cp110_comphy_sata_power_on()
403 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in mvebu_cp110_comphy_sata_power_on()
405 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
417 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; in mvebu_cp110_comphy_sata_power_on()
420 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; in mvebu_cp110_comphy_sata_power_on()
422 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
433 mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; in mvebu_cp110_comphy_sata_power_on()
436 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK; in mvebu_cp110_comphy_sata_power_on()
439 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK; in mvebu_cp110_comphy_sata_power_on()
442 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK; in mvebu_cp110_comphy_sata_power_on()
445 mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK; in mvebu_cp110_comphy_sata_power_on()
447 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
449 mask = HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK; in mvebu_cp110_comphy_sata_power_on()
451 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK; in mvebu_cp110_comphy_sata_power_on()
453 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; in mvebu_cp110_comphy_sata_power_on()
455 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK; in mvebu_cp110_comphy_sata_power_on()
457 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK; in mvebu_cp110_comphy_sata_power_on()
459 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
462 mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK; in mvebu_cp110_comphy_sata_power_on()
465 mask |= HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK; in mvebu_cp110_comphy_sata_power_on()
468 mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK; in mvebu_cp110_comphy_sata_power_on()
471 mask |= HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK; in mvebu_cp110_comphy_sata_power_on()
474 mask |= HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK; in mvebu_cp110_comphy_sata_power_on()
476 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
479 mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK; in mvebu_cp110_comphy_sata_power_on()
482 mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK; in mvebu_cp110_comphy_sata_power_on()
485 mask |= HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK; in mvebu_cp110_comphy_sata_power_on()
488 mask |= HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK; in mvebu_cp110_comphy_sata_power_on()
491 mask |= HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK; in mvebu_cp110_comphy_sata_power_on()
493 mask |= HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK; in mvebu_cp110_comphy_sata_power_on()
495 mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK; in mvebu_cp110_comphy_sata_power_on()
497 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
500 mask = HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK; in mvebu_cp110_comphy_sata_power_on()
502 mask |= HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK; in mvebu_cp110_comphy_sata_power_on()
504 mask |= HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; in mvebu_cp110_comphy_sata_power_on()
506 mask |= HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK; in mvebu_cp110_comphy_sata_power_on()
508 mask |= HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK; in mvebu_cp110_comphy_sata_power_on()
510 mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_MASK; in mvebu_cp110_comphy_sata_power_on()
512 mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK; in mvebu_cp110_comphy_sata_power_on()
514 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
517 mask = HPIPE_SMAPLER_MASK; in mvebu_cp110_comphy_sata_power_on()
519 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
520 mask = HPIPE_SMAPLER_MASK; in mvebu_cp110_comphy_sata_power_on()
522 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
525 mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; in mvebu_cp110_comphy_sata_power_on()
527 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
530 mask = HPIPE_DFE_RES_FORCE_MASK; in mvebu_cp110_comphy_sata_power_on()
532 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in mvebu_cp110_comphy_sata_power_on()
535 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; in mvebu_cp110_comphy_sata_power_on()
537 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; in mvebu_cp110_comphy_sata_power_on()
539 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
542 mask = HPIPE_G3_FFE_CAP_SEL_MASK; in mvebu_cp110_comphy_sata_power_on()
545 mask |= HPIPE_G3_FFE_RES_SEL_MASK; in mvebu_cp110_comphy_sata_power_on()
548 mask |= HPIPE_G3_FFE_SETTING_FORCE_MASK; in mvebu_cp110_comphy_sata_power_on()
550 mask |= HPIPE_G3_FFE_DEG_RES_LEVEL_MASK; in mvebu_cp110_comphy_sata_power_on()
552 mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK; in mvebu_cp110_comphy_sata_power_on()
554 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
557 mask = HPIPE_G3_DFE_RES_MASK; in mvebu_cp110_comphy_sata_power_on()
559 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
562 mask = HPIPE_OS_PH_OFFSET_MASK; in mvebu_cp110_comphy_sata_power_on()
564 mask |= HPIPE_OS_PH_OFFSET_FORCE_MASK; in mvebu_cp110_comphy_sata_power_on()
566 mask |= HPIPE_OS_PH_VALID_MASK; in mvebu_cp110_comphy_sata_power_on()
568 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
569 mask = HPIPE_OS_PH_VALID_MASK; in mvebu_cp110_comphy_sata_power_on()
571 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
572 mask = HPIPE_OS_PH_VALID_MASK; in mvebu_cp110_comphy_sata_power_on()
574 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
577 mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK; in mvebu_cp110_comphy_sata_power_on()
579 mask |= HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK; in mvebu_cp110_comphy_sata_power_on()
582 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; in mvebu_cp110_comphy_sata_power_on()
585 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK; in mvebu_cp110_comphy_sata_power_on()
588 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
591 mask = HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK; in mvebu_cp110_comphy_sata_power_on()
594 mask |= HPIPE_G1_SET_2_G1_TX_EMPH0_MASK; in mvebu_cp110_comphy_sata_power_on()
597 reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
600 mask = HPIPE_G2_SET_0_G2_TX_AMP_MASK; in mvebu_cp110_comphy_sata_power_on()
602 mask |= HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK; in mvebu_cp110_comphy_sata_power_on()
605 mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_MASK; in mvebu_cp110_comphy_sata_power_on()
608 mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK; in mvebu_cp110_comphy_sata_power_on()
611 reg_set(hpipe_addr + HPIPE_G2_SET_0_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
614 mask = HPIPE_G2_SET_2_G2_TX_EMPH0_EN_MASK; in mvebu_cp110_comphy_sata_power_on()
617 mask |= HPIPE_G2_SET_2_G2_TX_EMPH0_MASK; in mvebu_cp110_comphy_sata_power_on()
620 reg_set(hpipe_addr + HPIPE_G2_SET_2_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
623 mask = HPIPE_G3_SET_0_G3_TX_AMP_MASK; in mvebu_cp110_comphy_sata_power_on()
625 mask |= HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK; in mvebu_cp110_comphy_sata_power_on()
628 mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_MASK; in mvebu_cp110_comphy_sata_power_on()
631 mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK; in mvebu_cp110_comphy_sata_power_on()
634 mask |= HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK; in mvebu_cp110_comphy_sata_power_on()
636 mask |= HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK; in mvebu_cp110_comphy_sata_power_on()
638 reg_set(hpipe_addr + HPIPE_G3_SET_0_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
641 mask = HPIPE_G3_SET_2_G3_TX_EMPH0_EN_MASK; in mvebu_cp110_comphy_sata_power_on()
644 mask |= HPIPE_G3_SET_2_G3_TX_EMPH0_MASK; in mvebu_cp110_comphy_sata_power_on()
647 reg_set(hpipe_addr + HPIPE_G3_SET_2_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
650 mask = SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK; in mvebu_cp110_comphy_sata_power_on()
652 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
683 uint32_t mask, data, sgmii_speed = COMPHY_GET_SPEED(comphy_mode); in mvebu_cp110_comphy_sgmii_power_on() local
701 mask = COMMON_PHY_CFG1_PWR_UP_MASK; in mvebu_cp110_comphy_sgmii_power_on()
703 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; in mvebu_cp110_comphy_sgmii_power_on()
705 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
708 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; in mvebu_cp110_comphy_sgmii_power_on()
710 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; in mvebu_cp110_comphy_sgmii_power_on()
711 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; in mvebu_cp110_comphy_sgmii_power_on()
727 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; in mvebu_cp110_comphy_sgmii_power_on()
729 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; in mvebu_cp110_comphy_sgmii_power_on()
731 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; in mvebu_cp110_comphy_sgmii_power_on()
733 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
736 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in mvebu_cp110_comphy_sgmii_power_on()
738 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in mvebu_cp110_comphy_sgmii_power_on()
740 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; in mvebu_cp110_comphy_sgmii_power_on()
742 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
745 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in mvebu_cp110_comphy_sgmii_power_on()
747 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in mvebu_cp110_comphy_sgmii_power_on()
749 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
757 mask = COMMON_PHY_CFG6_IF_40_SEL_MASK; in mvebu_cp110_comphy_sgmii_power_on()
759 reg_set(comphy_addr + COMMON_PHY_CFG6_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
764 mask = HPIPE_MISC_REFCLK_SEL_MASK; in mvebu_cp110_comphy_sgmii_power_on()
766 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
768 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; in mvebu_cp110_comphy_sgmii_power_on()
770 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; in mvebu_cp110_comphy_sgmii_power_on()
772 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
774 mask = HPIPE_LOOPBACK_SEL_MASK; in mvebu_cp110_comphy_sgmii_power_on()
776 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
778 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; in mvebu_cp110_comphy_sgmii_power_on()
780 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; in mvebu_cp110_comphy_sgmii_power_on()
782 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
784 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; in mvebu_cp110_comphy_sgmii_power_on()
786 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
797 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; in mvebu_cp110_comphy_sgmii_power_on()
799 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; in mvebu_cp110_comphy_sgmii_power_on()
801 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; in mvebu_cp110_comphy_sgmii_power_on()
803 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
810 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; in mvebu_cp110_comphy_sgmii_power_on()
812 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
817 mask = data; in mvebu_cp110_comphy_sgmii_power_on()
818 data = polling_with_timeout(addr, data, mask, 100, REG_32BIT); in mvebu_cp110_comphy_sgmii_power_on()
826 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; in mvebu_cp110_comphy_sgmii_power_on()
828 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; in mvebu_cp110_comphy_sgmii_power_on()
830 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
843 uint32_t mask, data, speed = COMPHY_GET_SPEED(comphy_mode); in mvebu_cp110_comphy_xfi_power_on() local
894 mask = COMMON_PHY_CFG1_PWR_UP_MASK; in mvebu_cp110_comphy_xfi_power_on()
896 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; in mvebu_cp110_comphy_xfi_power_on()
898 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
903 mask = COMMON_PHY_CFG6_IF_40_SEL_MASK; in mvebu_cp110_comphy_xfi_power_on()
905 reg_set(comphy_addr + COMMON_PHY_CFG6_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
908 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; in mvebu_cp110_comphy_xfi_power_on()
910 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; in mvebu_cp110_comphy_xfi_power_on()
912 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; in mvebu_cp110_comphy_xfi_power_on()
914 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; in mvebu_cp110_comphy_xfi_power_on()
916 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; in mvebu_cp110_comphy_xfi_power_on()
918 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; in mvebu_cp110_comphy_xfi_power_on()
920 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
923 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in mvebu_cp110_comphy_xfi_power_on()
925 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in mvebu_cp110_comphy_xfi_power_on()
927 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; in mvebu_cp110_comphy_xfi_power_on()
929 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
931 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in mvebu_cp110_comphy_xfi_power_on()
933 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in mvebu_cp110_comphy_xfi_power_on()
935 mask |= SD_EXTERNAL_CONFIG1_TX_IDLE_MASK; in mvebu_cp110_comphy_xfi_power_on()
937 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
946 mask = SD_EXTERNAL_CONFIG1_TX_IDLE_MASK; in mvebu_cp110_comphy_xfi_power_on()
948 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
953 mask = HPIPE_MISC_ICP_FORCE_MASK; in mvebu_cp110_comphy_xfi_power_on()
957 mask |= HPIPE_MISC_REFCLK_SEL_MASK; in mvebu_cp110_comphy_xfi_power_on()
959 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
961 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; in mvebu_cp110_comphy_xfi_power_on()
963 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; in mvebu_cp110_comphy_xfi_power_on()
965 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
967 mask = HPIPE_LOOPBACK_SEL_MASK; in mvebu_cp110_comphy_xfi_power_on()
969 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
971 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; in mvebu_cp110_comphy_xfi_power_on()
973 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; in mvebu_cp110_comphy_xfi_power_on()
975 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
977 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; in mvebu_cp110_comphy_xfi_power_on()
979 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
983 mask = HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK; in mvebu_cp110_comphy_xfi_power_on()
985 mask |= HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK; in mvebu_cp110_comphy_xfi_power_on()
987 mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK; in mvebu_cp110_comphy_xfi_power_on()
989 mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK; in mvebu_cp110_comphy_xfi_power_on()
992 mask = HPIPE_TXDIGCK_DIV_FORCE_MASK; in mvebu_cp110_comphy_xfi_power_on()
995 reg_set(hpipe_addr + HPIPE_SPD_DIV_FORCE_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1000 mask = SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK; in mvebu_cp110_comphy_xfi_power_on()
1002 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1004 mask = HPIPE_DFE_RES_FORCE_MASK; in mvebu_cp110_comphy_xfi_power_on()
1006 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1009 mask = HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; in mvebu_cp110_comphy_xfi_power_on()
1012 mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK; in mvebu_cp110_comphy_xfi_power_on()
1015 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; in mvebu_cp110_comphy_xfi_power_on()
1019 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK; in mvebu_cp110_comphy_xfi_power_on()
1022 mask |= HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK; in mvebu_cp110_comphy_xfi_power_on()
1026 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1028 mask = HPIPE_G1_SET_2_G1_TX_EMPH0_MASK; in mvebu_cp110_comphy_xfi_power_on()
1031 mask |= HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK; in mvebu_cp110_comphy_xfi_power_on()
1034 reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1036 mask = HPIPE_TX_REG1_TX_EMPH_RES_MASK; in mvebu_cp110_comphy_xfi_power_on()
1038 mask |= HPIPE_TX_REG1_SLC_EN_MASK; in mvebu_cp110_comphy_xfi_power_on()
1040 reg_set(hpipe_addr + HPIPE_TX_REG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1042 mask = HPIPE_CAL_REG_1_EXT_TXIMP_MASK; in mvebu_cp110_comphy_xfi_power_on()
1044 mask |= HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK; in mvebu_cp110_comphy_xfi_power_on()
1046 reg_set(hpipe_addr + HPIPE_CAL_REG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1048 mask = HPIPE_G1_SETTING_5_G1_ICP_MASK; in mvebu_cp110_comphy_xfi_power_on()
1050 reg_set(hpipe_addr + HPIPE_G1_SETTING_5_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1053 mask = HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK; in mvebu_cp110_comphy_xfi_power_on()
1056 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; in mvebu_cp110_comphy_xfi_power_on()
1058 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK; in mvebu_cp110_comphy_xfi_power_on()
1061 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; in mvebu_cp110_comphy_xfi_power_on()
1064 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK; in mvebu_cp110_comphy_xfi_power_on()
1067 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK; in mvebu_cp110_comphy_xfi_power_on()
1070 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK; in mvebu_cp110_comphy_xfi_power_on()
1073 mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK; in mvebu_cp110_comphy_xfi_power_on()
1076 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1079 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; in mvebu_cp110_comphy_xfi_power_on()
1081 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; in mvebu_cp110_comphy_xfi_power_on()
1083 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1086 mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK; in mvebu_cp110_comphy_xfi_power_on()
1088 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1090 mask = HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK; in mvebu_cp110_comphy_xfi_power_on()
1094 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK; in mvebu_cp110_comphy_xfi_power_on()
1096 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK; in mvebu_cp110_comphy_xfi_power_on()
1098 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; in mvebu_cp110_comphy_xfi_power_on()
1100 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1102 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK; in mvebu_cp110_comphy_xfi_power_on()
1105 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK; in mvebu_cp110_comphy_xfi_power_on()
1108 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; in mvebu_cp110_comphy_xfi_power_on()
1110 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1113 mask = HPIPE_CAL_RXCLKALIGN_90_EXT_EN_MASK; in mvebu_cp110_comphy_xfi_power_on()
1117 data, mask); in mvebu_cp110_comphy_xfi_power_on()
1120 mask = HPIPE_CAL_OS_PH_EXT_MASK; in mvebu_cp110_comphy_xfi_power_on()
1124 data, mask); in mvebu_cp110_comphy_xfi_power_on()
1127 mask = HPIPE_DFE_RES_FORCE_MASK; in mvebu_cp110_comphy_xfi_power_on()
1129 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1132 mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK; in mvebu_cp110_comphy_xfi_power_on()
1135 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1139 mask = HPIPE_RX_TRAIN_TIMER_MASK; in mvebu_cp110_comphy_xfi_power_on()
1141 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1144 mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK; in mvebu_cp110_comphy_xfi_power_on()
1146 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1149 mask = HPIPE_TX_PRESET_INDEX_MASK; in mvebu_cp110_comphy_xfi_power_on()
1151 reg_set(hpipe_addr + HPIPE_TX_PRESET_INDEX_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1154 mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK; in mvebu_cp110_comphy_xfi_power_on()
1156 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1159 mask = HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK; in mvebu_cp110_comphy_xfi_power_on()
1161 mask |= HPIPE_TX_TRAIN_PAT_SEL_MASK; in mvebu_cp110_comphy_xfi_power_on()
1163 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1166 mask = HPIPE_TRAIN_PAT_NUM_MASK; in mvebu_cp110_comphy_xfi_power_on()
1168 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_0_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1171 mask = HPIPE_DME_ETHERNET_MODE_MASK; in mvebu_cp110_comphy_xfi_power_on()
1173 reg_set(hpipe_addr + HPIPE_DME_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1176 mask = HPIPE_CAL_VDD_CONT_MODE_MASK; in mvebu_cp110_comphy_xfi_power_on()
1178 reg_set(hpipe_addr + HPIPE_VDD_CAL_0_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1181 mask = HPIPE_RX_SAMPLER_OS_GAIN_MASK; in mvebu_cp110_comphy_xfi_power_on()
1183 mask |= HPIPE_SMAPLER_MASK; in mvebu_cp110_comphy_xfi_power_on()
1185 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1186 mask = HPIPE_SMAPLER_MASK; in mvebu_cp110_comphy_xfi_power_on()
1188 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1191 mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; in mvebu_cp110_comphy_xfi_power_on()
1193 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1197 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; in mvebu_cp110_comphy_xfi_power_on()
1199 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; in mvebu_cp110_comphy_xfi_power_on()
1201 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; in mvebu_cp110_comphy_xfi_power_on()
1203 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1209 mask = data; in mvebu_cp110_comphy_xfi_power_on()
1210 data = polling_with_timeout(addr, data, mask, in mvebu_cp110_comphy_xfi_power_on()
1222 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; in mvebu_cp110_comphy_xfi_power_on()
1224 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1229 mask = data; in mvebu_cp110_comphy_xfi_power_on()
1230 data = polling_with_timeout(addr, data, mask, 100, REG_32BIT); in mvebu_cp110_comphy_xfi_power_on()
1238 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; in mvebu_cp110_comphy_xfi_power_on()
1240 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; in mvebu_cp110_comphy_xfi_power_on()
1242 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1261 uint32_t reg, mask, data, pcie_width; in mvebu_cp110_comphy_pcie_power_on() local
1337 mask = COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1339 data, mask); in mvebu_cp110_comphy_pcie_power_on()
1342 mask = COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1343 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1354 mask = DFX_DEV_GEN_PCIE_CLK_SRC_MASK; in mvebu_cp110_comphy_pcie_power_on()
1356 DFX_DEV_GEN_CTRL12_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1361 mask = COMMON_PHY_CFG1_PWR_UP_MASK; in mvebu_cp110_comphy_pcie_power_on()
1363 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; in mvebu_cp110_comphy_pcie_power_on()
1365 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; in mvebu_cp110_comphy_pcie_power_on()
1367 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1369 mask |= COMMON_PHY_PHY_MODE_MASK; in mvebu_cp110_comphy_pcie_power_on()
1371 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1374 mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; in mvebu_cp110_comphy_pcie_power_on()
1376 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1378 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1385 mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; in mvebu_cp110_comphy_pcie_power_on()
1388 mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; in mvebu_cp110_comphy_pcie_power_on()
1391 mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; in mvebu_cp110_comphy_pcie_power_on()
1394 mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; in mvebu_cp110_comphy_pcie_power_on()
1396 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1399 mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK; in mvebu_cp110_comphy_pcie_power_on()
1402 mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK; in mvebu_cp110_comphy_pcie_power_on()
1404 mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK; in mvebu_cp110_comphy_pcie_power_on()
1406 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1410 mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK; in mvebu_cp110_comphy_pcie_power_on()
1412 mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK; in mvebu_cp110_comphy_pcie_power_on()
1413 mask |= HPIPE_CLK_SRC_HI_LANE_MASTER_MASK; in mvebu_cp110_comphy_pcie_power_on()
1414 mask |= HPIPE_CLK_SRC_HI_LANE_BREAK_MASK; in mvebu_cp110_comphy_pcie_power_on()
1422 reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1425 mask = HPIPE_CFG_UPDATE_POLARITY_MASK; in mvebu_cp110_comphy_pcie_power_on()
1426 reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG1_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1429 mask = HPIPE_DFE_CTRL_28_PIPE4_MASK; in mvebu_cp110_comphy_pcie_power_on()
1430 reg_set(hpipe_addr + HPIPE_DFE_CTRL_28_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1433 mask = 0; in mvebu_cp110_comphy_pcie_power_on()
1437 mask |= HPIPE_MISC_CLK100M_125M_MASK; in mvebu_cp110_comphy_pcie_power_on()
1441 mask |= HPIPE_MISC_TXDCLK_2X_MASK; in mvebu_cp110_comphy_pcie_power_on()
1444 mask |= HPIPE_MISC_CLK500_EN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1448 mask |= HPIPE_MISC_REFCLK_SEL_MASK; in mvebu_cp110_comphy_pcie_power_on()
1452 mask |= HPIPE_MISC_REFCLK_SEL_MASK; in mvebu_cp110_comphy_pcie_power_on()
1455 mask |= HPIPE_MISC_ICP_FORCE_MASK; in mvebu_cp110_comphy_pcie_power_on()
1457 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1460 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; in mvebu_cp110_comphy_pcie_power_on()
1464 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; in mvebu_cp110_comphy_pcie_power_on()
1468 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; in mvebu_cp110_comphy_pcie_power_on()
1470 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1474 mask = HPIPE_LANE_ALIGN_OFF_MASK; in mvebu_cp110_comphy_pcie_power_on()
1476 reg_set(hpipe_addr + HPIPE_LANE_ALIGN_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1488 mask = HPIPE_INTERFACE_GEN_MAX_MASK; in mvebu_cp110_comphy_pcie_power_on()
1491 mask |= HPIPE_INTERFACE_DET_BYPASS_MASK; in mvebu_cp110_comphy_pcie_power_on()
1494 mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1496 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1499 mask = HPIPE_PCIE_IDLE_SYNC_MASK; in mvebu_cp110_comphy_pcie_power_on()
1502 mask |= HPIPE_PCIE_SEL_BITS_MASK; in mvebu_cp110_comphy_pcie_power_on()
1504 reg_set(hpipe_addr + HPIPE_PCIE_REG0, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1507 mask = HPIPE_TX_TRAIN_CTRL_G1_MASK; in mvebu_cp110_comphy_pcie_power_on()
1510 mask |= HPIPE_TX_TRAIN_CTRL_GN1_MASK; in mvebu_cp110_comphy_pcie_power_on()
1513 mask |= HPIPE_TX_TRAIN_CTRL_G0_MASK; in mvebu_cp110_comphy_pcie_power_on()
1515 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1518 mask = HPIPE_TX_TRAIN_CHK_INIT_MASK; in mvebu_cp110_comphy_pcie_power_on()
1521 mask |= HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK; in mvebu_cp110_comphy_pcie_power_on()
1523 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1527 mask = HPIPE_TX_TX_STATUS_CHECK_MODE_MASK; in mvebu_cp110_comphy_pcie_power_on()
1529 mask |= HPIPE_TX_NUM_OF_PRESET_MASK; in mvebu_cp110_comphy_pcie_power_on()
1531 mask |= HPIPE_TX_SWEEP_PRESET_EN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1533 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_11_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1536 mask = HPIPE_TX_TRAIN_START_SQ_EN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1538 mask |= HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1540 mask |= HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1542 mask |= HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1544 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1547 mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK; in mvebu_cp110_comphy_pcie_power_on()
1549 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1552 mask = HPIPE_TRX_TRAIN_TIMER_MASK; in mvebu_cp110_comphy_pcie_power_on()
1554 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_4_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1557 mask = HPIPE_TX_TRAIN_CTRL_G1_MASK | HPIPE_TX_TRAIN_CTRL_GN1_MASK in mvebu_cp110_comphy_pcie_power_on()
1560 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1563 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1565 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1568 mask = HPIPE_G3_DFE_RES_MASK; in mvebu_cp110_comphy_pcie_power_on()
1570 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1573 mask = HPIPE_DFE_RES_FORCE_MASK; in mvebu_cp110_comphy_pcie_power_on()
1575 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1578 mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK; in mvebu_cp110_comphy_pcie_power_on()
1581 mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK; in mvebu_cp110_comphy_pcie_power_on()
1584 mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1586 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1589 mask = HPIPE_SMAPLER_MASK; in mvebu_cp110_comphy_pcie_power_on()
1591 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1593 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, 0, mask); in mvebu_cp110_comphy_pcie_power_on()
1596 mask = HPIPE_G3_FFE_DEG_RES_LEVEL_MASK; in mvebu_cp110_comphy_pcie_power_on()
1598 mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK; in mvebu_cp110_comphy_pcie_power_on()
1600 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1603 mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1605 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1608 mask = HPIPE_CDR_RX_MAX_DFE_ADAPT_0_MASK; in mvebu_cp110_comphy_pcie_power_on()
1610 mask |= HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK; in mvebu_cp110_comphy_pcie_power_on()
1612 mask |= HPIPE_CDR_MAX_DFE_ADAPT_0_MASK; in mvebu_cp110_comphy_pcie_power_on()
1614 mask |= HPIPE_CDR_MAX_DFE_ADAPT_1_MASK; in mvebu_cp110_comphy_pcie_power_on()
1616 reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1618 mask = HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK; in mvebu_cp110_comphy_pcie_power_on()
1620 reg_set(hpipe_addr + HPIPE_DFE_CONTROL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1623 mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK; in mvebu_cp110_comphy_pcie_power_on()
1625 mask |= HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK; in mvebu_cp110_comphy_pcie_power_on()
1627 mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK; in mvebu_cp110_comphy_pcie_power_on()
1629 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1632 mask = HPIPE_G2_DFE_RES_MASK; in mvebu_cp110_comphy_pcie_power_on()
1634 reg_set(hpipe_addr + HPIPE_G2_SETTINGS_4_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1637 mask = HPIPE_LANE_CFG4_DFE_EN_SEL_MASK; in mvebu_cp110_comphy_pcie_power_on()
1639 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1642 mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; in mvebu_cp110_comphy_pcie_power_on()
1644 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1647 mask = HPIPE_G3_SETTING_5_G3_ICP_MASK; in mvebu_cp110_comphy_pcie_power_on()
1649 reg_set(hpipe_addr + HPIPE_G3_SETTING_5_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1652 mask = HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK; in mvebu_cp110_comphy_pcie_power_on()
1654 mask |= HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK; in mvebu_cp110_comphy_pcie_power_on()
1656 mask |= HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK; in mvebu_cp110_comphy_pcie_power_on()
1658 reg_set(hpipe_addr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1660 mask = HPIPE_CFG_EQ_BUNDLE_DIS_MASK; in mvebu_cp110_comphy_pcie_power_on()
1662 reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG2_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1676 mask = COMMON_PHY_SD_CTRL1_COMPHY_0_1_PORT_MASK; in mvebu_cp110_comphy_pcie_power_on()
1678 mask = COMMON_PHY_SD_CTRL1_COMPHY_0_3_PORT_MASK; in mvebu_cp110_comphy_pcie_power_on()
1679 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1711 mask = COMMON_PHY_SD_CTRL1_COMPHY_0_1_PORT_MASK; in mvebu_cp110_comphy_pcie_power_on()
1721 mask = COMMON_PHY_SD_CTRL1_COMPHY_0_3_PORT_MASK; in mvebu_cp110_comphy_pcie_power_on()
1724 data, mask); in mvebu_cp110_comphy_pcie_power_on()
1734 mask = data; in mvebu_cp110_comphy_pcie_power_on()
1735 data = polling_with_timeout(addr, data, mask, in mvebu_cp110_comphy_pcie_power_on()
1754 uint32_t mask, data; in mvebu_cp110_comphy_rxaui_power_on() local
1770 mask = COMMON_PHY_CFG1_PWR_UP_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1772 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1774 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1788 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1790 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1792 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1794 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1796 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1798 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1800 mask |= SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1802 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1805 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1807 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1809 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1811 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1813 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1815 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1817 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1829 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1831 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1833 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1838 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1840 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1842 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1862 mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1864 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1866 mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1868 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1870 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1872 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1874 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1877 mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1879 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1883 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1885 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1887 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1889 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1896 mask = data; in mvebu_cp110_comphy_rxaui_power_on()
1897 data = polling_with_timeout(addr, data, mask, 15000, REG_32BIT); in mvebu_cp110_comphy_rxaui_power_on()
1915 mask = data; in mvebu_cp110_comphy_rxaui_power_on()
1916 data = polling_with_timeout(addr, data, mask, 100, REG_32BIT); in mvebu_cp110_comphy_rxaui_power_on()
1926 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1928 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1930 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1941 uint32_t mask, data; in mvebu_cp110_comphy_usb3_power_on() local
1964 mask = COMMON_PHY_CFG1_PWR_UP_MASK; in mvebu_cp110_comphy_usb3_power_on()
1966 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; in mvebu_cp110_comphy_usb3_power_on()
1968 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; in mvebu_cp110_comphy_usb3_power_on()
1970 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; in mvebu_cp110_comphy_usb3_power_on()
1972 mask |= COMMON_PHY_PHY_MODE_MASK; in mvebu_cp110_comphy_usb3_power_on()
1974 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_usb3_power_on()
1977 mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; in mvebu_cp110_comphy_usb3_power_on()
1979 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; in mvebu_cp110_comphy_usb3_power_on()
1981 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_usb3_power_on()
1989 mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; in mvebu_cp110_comphy_usb3_power_on()
1992 mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; in mvebu_cp110_comphy_usb3_power_on()
1995 mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; in mvebu_cp110_comphy_usb3_power_on()
1998 mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; in mvebu_cp110_comphy_usb3_power_on()
2000 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); in mvebu_cp110_comphy_usb3_power_on()
2010 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; in mvebu_cp110_comphy_usb3_power_on()
2013 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; in mvebu_cp110_comphy_usb3_power_on()
2015 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in mvebu_cp110_comphy_usb3_power_on()
2047 mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK; in mvebu_cp110_comphy_usb3_power_on()
2050 mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK; in mvebu_cp110_comphy_usb3_power_on()
2053 mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK; in mvebu_cp110_comphy_usb3_power_on()
2055 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); in mvebu_cp110_comphy_usb3_power_on()
2057 mask = HPIPE_G2_TX_SSC_AMP_MASK; in mvebu_cp110_comphy_usb3_power_on()
2059 reg_set(hpipe_addr + HPIPE_G2_SET_2_REG, data, mask); in mvebu_cp110_comphy_usb3_power_on()
2073 mask = data; in mvebu_cp110_comphy_usb3_power_on()
2074 data = polling_with_timeout(addr, data, mask, 15000, REG_32BIT); in mvebu_cp110_comphy_usb3_power_on()
2090 uint32_t mask, data; in rx_pre_train() local
2097 mask = HPIPE_TRX0_GAIN_TRAIN_WITH_C_MASK; in rx_pre_train()
2099 mask |= HPIPE_TRX0_GAIN_TRAIN_WITH_SAMPLER_MASK; in rx_pre_train()
2101 reg_set(hpipe_addr + HPIPE_TRX0_REG, data, mask); in rx_pre_train()
2104 mask = HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_MASK; in rx_pre_train()
2106 mask |= HPIPE_TRX_REG2_SUMF_BOOST_TARGET_K_MASK; in rx_pre_train()
2108 reg_set(hpipe_addr + HPIPE_TRX_REG2, data, mask); in rx_pre_train()
2110 mask = HPIPE_TRX_REG1_MIN_BOOST_MODE_MASK; in rx_pre_train()
2112 reg_set(hpipe_addr + HPIPE_TRX_REG1, data, mask); in rx_pre_train()
2114 mask = HPIPE_CRD2_CRD_MIDPOINT_SMALL_THRES_K_MASK; in rx_pre_train()
2116 reg_set(hpipe_addr + HPIPE_CDR_CONTROL1_REG, data, mask); in rx_pre_train()
2118 mask = HPIPE_CRD2_CRD_MIDPOINT_LARGE_THRES_K_MASK; in rx_pre_train()
2120 reg_set(hpipe_addr + HPIPE_CDR_CONTROL2_REG, data, mask); in rx_pre_train()
2122 mask = HPIPE_CRD_MIDPOINT_PHASE_OS_MASK; in rx_pre_train()
2124 reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask); in rx_pre_train()
2126 mask = HPIPE_TRX_REG1_SUMFTAP_EN_MASK; in rx_pre_train()
2128 mask |= HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_MASK; in rx_pre_train()
2130 reg_set(hpipe_addr + HPIPE_TRX_REG1, data, mask); in rx_pre_train()
2136 uint32_t mask, data, timeout; in mvebu_cp110_comphy_xfi_rx_training() local
2154 mask = HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; in mvebu_cp110_comphy_xfi_rx_training()
2156 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2159 mask = HPIPE_CAL_RXCLKALIGN_90_EXT_EN_MASK; in mvebu_cp110_comphy_xfi_rx_training()
2162 data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2165 mask = HPIPE_DFE_RES_FORCE_MASK; in mvebu_cp110_comphy_xfi_rx_training()
2167 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2171 mask = HPIPE_TRX_RX_TRAIN_EN_MASK; in mvebu_cp110_comphy_xfi_rx_training()
2173 reg_set(hpipe_addr + HPIPE_TRX_TRAIN_CTRL_0_REG, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2177 mask = HPIPE_INTERRUPT_TRX_TRAIN_DONE_OFFSET | in mvebu_cp110_comphy_xfi_rx_training()
2182 if (data & mask) in mvebu_cp110_comphy_xfi_rx_training()
2201 mask = HPIPE_TRX_RX_TRAIN_EN_MASK; in mvebu_cp110_comphy_xfi_rx_training()
2203 reg_set(hpipe_addr + HPIPE_TRX_TRAIN_CTRL_0_REG, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2207 mask = HPIPE_ADAPTED_FFE_ADAPTED_FFE_RES_MASK; in mvebu_cp110_comphy_xfi_rx_training()
2210 & mask) >> HPIPE_ADAPTED_FFE_ADAPTED_FFE_RES_OFFSET); in mvebu_cp110_comphy_xfi_rx_training()
2212 mask = HPIPE_ADAPTED_FFE_ADAPTED_FFE_CAP_MASK; in mvebu_cp110_comphy_xfi_rx_training()
2215 & mask) >> HPIPE_ADAPTED_FFE_ADAPTED_FFE_CAP_OFFSET); in mvebu_cp110_comphy_xfi_rx_training()
2217 mask = HPIPE_DATA_PHASE_ADAPTED_OS_PH_MASK; in mvebu_cp110_comphy_xfi_rx_training()
2219 & mask) >> HPIPE_DATA_PHASE_ADAPTED_OS_PH_OFFSET); in mvebu_cp110_comphy_xfi_rx_training()
2221 mask = HPIPE_ADAPTED_DFE_RES_MASK; in mvebu_cp110_comphy_xfi_rx_training()
2224 & mask) >> HPIPE_ADAPTED_DFE_RES_OFFSET); in mvebu_cp110_comphy_xfi_rx_training()
2241 mask = HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK; in mvebu_cp110_comphy_xfi_rx_training()
2243 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2246 mask = HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK; in mvebu_cp110_comphy_xfi_rx_training()
2248 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2253 mask = HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; in mvebu_cp110_comphy_xfi_rx_training()
2255 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2258 mask = HPIPE_DFE_RES_FORCE_MASK; in mvebu_cp110_comphy_xfi_rx_training()
2260 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2263 mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK; in mvebu_cp110_comphy_xfi_rx_training()
2265 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2303 uint32_t mask, data; in mvebu_cp110_comphy_ap_power_on() local
2313 mask = COMMON_PHY_CFG1_PWR_UP_MASK; in mvebu_cp110_comphy_ap_power_on()
2315 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; in mvebu_cp110_comphy_ap_power_on()
2317 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_ap_power_on()
2343 uint32_t mask, data; in mvebu_cp110_comphy_digital_reset() local
2354 mask = SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; in mvebu_cp110_comphy_digital_reset()
2357 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_digital_reset()
2433 uint32_t mask, data; in mvebu_cp110_comphy_power_off() local
2481 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in mvebu_cp110_comphy_power_off()
2483 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in mvebu_cp110_comphy_power_off()
2485 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; in mvebu_cp110_comphy_power_off()
2487 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_power_off()
2515 mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; in mvebu_cp110_comphy_power_off()
2517 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; in mvebu_cp110_comphy_power_off()
2519 reg_set(comphy_ip_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_power_off()