Lines Matching +full:- +full:cpu
1 Arm CPU Specific Build Macros
4 This document describes the various build options present in the CPU specific
6 for a specific CPU on a platform.
9 ----------------------------------
11 TF-A exports a series of build flags which control which security
14 - ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for
15 `CVE-2017-5715`_. This flag can be set to 0 by the platform if none
17 no performance benefit for non-affected platforms, it just helps to comply
21 - ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for
22 `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep
24 CVE-2018-3639, in order to comply with the recommendation in the spec
27 - ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for
28 `CVE-2018-3639`_. This build option should be set to 1 if the target
29 platform contains at least 1 CPU that requires dynamic mitigation.
34 CPU Errata Workarounds
35 ----------------------
37 TF-A exports a series of build flags which control the errata workarounds that
38 are applied to each CPU by the reset handler. The errata details can be found
39 in the CPU specific errata documents published by Arm:
41 - `Cortex-A53 MPCore Software Developers Errata Notice`_
42 - `Cortex-A57 MPCore Software Developers Errata Notice`_
43 - `Cortex-A72 MPCore Software Developers Errata Notice`_
50 is for example ``A57`` for the ``Cortex_A57`` CPU.
58 these workarounds are enabled for the wrong CPU revision then the errata
69 For Cortex-A9, the following errata build flags are defined :
71 - ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9
72 CPU. This needs to be enabled for all revisions of the CPU.
74 For Cortex-A15, the following errata build flags are defined :
76 - ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15
77 CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
79 - ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15
80 CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
82 For Cortex-A17, the following errata build flags are defined :
84 - ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17
85 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
87 - ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17
88 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
90 For Cortex-A35, the following errata build flags are defined :
92 - ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35
93 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35.
95 For Cortex-A53, the following errata build flags are defined :
97 - ``ERRATA_A53_819472``: This applies errata 819472 workaround to all
98 CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53.
100 - ``ERRATA_A53_824069``: This applies errata 824069 workaround to all
101 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
103 - ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53
104 CPU. This needs to be enabled only for revision <= r0p2 of the CPU.
106 - ``ERRATA_A53_827319``: This applies errata 827319 workaround to all
107 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
109 - ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and
110 link time to Cortex-A53 CPU. This needs to be enabled for some variants of
114 - ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53
115 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From
118 - ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time
119 to Cortex-A53 CPU. This needs to be enabled for some variants of revision
123 - ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53
124 CPUs. Though the erratum is present in every revision of the CPU,
127 Earlier revisions of the CPU have other errata which require the same
130 - ``ERRATA_A53_1530924``: This applies errata 1530924 workaround to all
131 revisions of Cortex-A53 CPU.
133 For Cortex-A55, the following errata build flags are defined :
135 - ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55
136 CPU. This needs to be enabled only for revision r0p0 of the CPU.
138 - ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55
139 CPU. This needs to be enabled only for revision r0p0 of the CPU.
141 - ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55
142 CPU. This needs to be enabled only for revision r0p0 of the CPU.
144 - ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55
145 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
147 - ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55
148 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
150 - ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55
151 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
153 - ``ERRATA_A55_1530923``: This applies errata 1530923 workaround to all
154 revisions of Cortex-A55 CPU.
156 For Cortex-A57, the following errata build flags are defined :
158 - ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57
159 CPU. This needs to be enabled only for revision r0p0 of the CPU.
161 - ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57
162 CPU. This needs to be enabled only for revision r0p0 of the CPU.
164 - ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57
165 CPU. This needs to be enabled only for revision r0p0 of the CPU.
167 - ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57
168 CPU. This needs to be enabled only for revision r0p0 of the CPU.
170 - ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57
171 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
173 - ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57
174 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
176 - ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57
177 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
179 - ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57
180 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
182 - ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57
183 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
185 - ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57
186 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
188 - ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57
189 CPU. This needs to be enabled only for revision <= r1p3 of the CPU.
191 - ``ERRATA_A57_1319537``: This applies errata 1319537 workaround to all
192 revisions of Cortex-A57 CPU.
194 For Cortex-A72, the following errata build flags are defined :
196 - ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72
197 CPU. This needs to be enabled only for revision <= r0p3 of the CPU.
199 - ``ERRATA_A72_1319367``: This applies errata 1319367 workaround to all
200 revisions of Cortex-A72 CPU.
202 For Cortex-A73, the following errata build flags are defined :
204 - ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73
205 CPU. This needs to be enabled only for revision r0p0 of the CPU.
207 - ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73
208 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
210 For Cortex-A75, the following errata build flags are defined :
212 - ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75
213 CPU. This needs to be enabled only for revision r0p0 of the CPU.
215 - ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75
216 CPU. This needs to be enabled only for revision r0p0 of the CPU.
218 For Cortex-A76, the following errata build flags are defined :
220 - ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76
221 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
223 - ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76
224 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
226 - ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76
227 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
229 - ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76
230 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
232 - ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76
233 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
235 - ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76
236 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
238 - ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76
239 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
241 - ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76
242 CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
244 - ``ERRATA_A76_1165522``: This applies errata 1165522 workaround to all
245 revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to
247 of Cortex-A76 CPU.
249 - ``ERRATA_A76_1868343``: This applies errata 1868343 workaround to Cortex-A76
250 CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
252 - ``ERRATA_A76_1946160``: This applies errata 1946160 workaround to Cortex-A76
253 CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU.
255 For Cortex-A77, the following errata build flags are defined :
257 - ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77
258 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
260 - ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77
261 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
263 - ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77
264 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
266 - ``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77
267 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
269 For Cortex-A78, the following errata build flags are defined :
271 - ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78
272 CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU.
274 - ``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78
275 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
277 - ``ERRATA_A78_1951500``: This applies errata 1951500 workaround to Cortex-A78
278 CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same
281 - ``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78
282 CPU. This needs to be enabled for revisions r0p0 and r1p0.
284 - ``ERRATA_A78_1952683``: This applies errata 1952683 workaround to Cortex-A78
285 CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0.
287 - ``ERRATA_A78_2132060``: This applies errata 2132060 workaround to Cortex-A78
288 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2. It
291 - ``ERRATA_A78_2242635``: This applies errata 2242635 workaround to Cortex-A78
292 CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue
295 For Cortex-A78 AE, the following errata build flags are defined :
297 - ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to Cortex-A78
298 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is
301 - ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to Cortex-A78
302 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is
307 - ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1
308 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU.
310 - ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1
311 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
313 - ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1
314 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
316 - ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1
317 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
319 - ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1
320 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
322 - ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1
323 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
325 - ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1
326 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
328 - ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1
329 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
331 - ``ERRATA_N1_1275112``: This applies errata 1275112 workaround to Neoverse-N1
332 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
334 - ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1
335 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
337 - ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1
338 CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU.
340 - ``ERRATA_N1_1868343``: This applies errata 1868343 workaround to Neoverse-N1
341 CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
343 - ``ERRATA_N1_1946160``: This applies errata 1946160 workaround to Neoverse-N1
344 CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for
349 - ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1
350 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
353 - ``ERRATA_V1_1791573``: This applies errata 1791573 workaround to Neoverse-V1
354 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
357 - ``ERRATA_V1_1852267``: This applies errata 1852267 workaround to Neoverse-V1
358 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
361 - ``ERRATA_V1_1925756``: This applies errata 1925756 workaround to Neoverse-V1
362 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
364 - ``ERRATA_V1_1940577``: This applies errata 1940577 workaround to Neoverse-V1
365 CPU. This needs to be enabled only for revision r1p0 and r1p1 of the
366 CPU.
368 - ``ERRATA_V1_1966096``: This applies errata 1966096 workaround to Neoverse-V1
369 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the
373 - ``ERRATA_V1_2139242``: This applies errata 2139242 workaround to Neoverse-V1
374 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the
375 CPU. It is still open.
377 - ``ERRATA_V1_2108267``: This applies errata 2108267 workaround to Neoverse-V1
378 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
381 - ``ERRATA_V1_2216392``: This applies errata 2216392 workaround to Neoverse-V1
382 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the
386 For Cortex-A710, the following errata build flags are defined :
388 - ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to
389 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
390 r2p0 of the CPU. It is still open.
392 - ``ERRATA_A710_2081180``: This applies errata 2081180 workaround to
393 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
394 r2p0 of the CPU. It is still open.
396 - ``ERRATA_A710_2055002``: This applies errata 2055002 workaround to
397 Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU
400 - ``ERRATA_A710_2017096``: This applies errata 2017096 workaround to
401 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
402 of the CPU and is still open.
404 - ``ERRATA_A710_2083908``: This applies errata 2083908 workaround to
405 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and
408 - ``ERRATA_A710_2058056``: This applies errata 2058056 workaround to
409 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
410 of the CPU and is still open.
414 - ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2
415 CPU. This needs to be enabled for revision r0p0 of the CPU, it is still open.
417 - ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2
418 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
420 - ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2
421 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
423 - ``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2
424 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
426 - ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2
427 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
429 - ``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2
430 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
432 - ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2
433 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
435 - ``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2
436 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
438 - ``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2
439 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
441 - ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2
442 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
445 ----------------------
447 Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ
451 - `Arm DSU Software Developers Errata Notice`_.
456 of DSU errata workarounds are similar to `CPU errata workarounds`_.
460 - ``ERRATA_DSU_798953``: This applies errata 798953 workaround for the
465 - ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the
471 CPU Specific optimizations
472 --------------------------
474 This section describes some of the optimizations allowed by the CPU micro
477 - ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the
478 Cortex-A57 cluster power down sequence by not flushing the Level 1 data
481 is a known safe deviation from the Cortex-A57 TRM defined power down
482 sequence. Each Cortex-A57 based platform must make its own decision on
485 - ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal
486 hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave
488 significant speed degradation to any code that employs them. The Armv8-A
490 the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this
492 <= r0p3 of the CPU and is enabled by default.
494 - ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as
495 ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be
496 enabled only for revisions <= r1p2 of the CPU and is enabled by default,
497 as recommended in section "4.7 Non-Temporal Loads/Stores" of the
498 `Cortex-A57 Software Optimization Guide`_.
500 - ''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable
501 streaming enhancement feature for Cortex-A57 CPUs. Platforms can set
503 line fill requests from the Cortex-A57 processor are atomic. Each
504 Cortex-A57 based platform must make its own decision on whether to use
507 - ``NEOVERSE_Nx_EXTERNAL_LLC``: This flag indicates that an external last
513 --------------
515 *Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.*
517 .. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715
518 .. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639
519 .. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.a…
520 .. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.a…
521 .. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.a…
522 .. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan001…