Lines Matching defs:input_offset
208 TEST(QU8_DWCONV_MINMAX_FP32_UP8X9__NEON_MUL16, input_offset) { in TEST() argument
422 TEST(QU8_DWCONV_MINMAX_FP32_UP8X9__NEONV8_MUL16, input_offset) { in TEST() argument
636 TEST(QU8_DWCONV_MINMAX_FP32_UP8X25__NEON_MUL16, input_offset) { in TEST() argument
850 TEST(QU8_DWCONV_MINMAX_FP32_UP8X25__NEONV8_MUL16, input_offset) { in TEST() argument
1064 TEST(QU8_DWCONV_MINMAX_FP32_UP16X9__NEON_MUL16, input_offset) { in TEST() argument
1278 TEST(QU8_DWCONV_MINMAX_FP32_UP16X9__NEONV8_MUL16, input_offset) { in TEST() argument
1492 TEST(QU8_DWCONV_MINMAX_FP32_UP16X25__NEON_MUL16, input_offset) { in TEST() argument
1706 TEST(QU8_DWCONV_MINMAX_FP32_UP16X25__NEONV8_MUL16, input_offset) { in TEST() argument
1920 TEST(QU8_DWCONV_MINMAX_FP32_UP24X9__NEON_MUL16, input_offset) { in TEST() argument
2134 TEST(QU8_DWCONV_MINMAX_FP32_UP24X9__NEONV8_MUL16, input_offset) { in TEST() argument
2348 TEST(QU8_DWCONV_MINMAX_FP32_UP24X25__NEON_MUL16, input_offset) { in TEST() argument
2562 TEST(QU8_DWCONV_MINMAX_FP32_UP24X25__NEONV8_MUL16, input_offset) { in TEST() argument
2776 TEST(QU8_DWCONV_MINMAX_FP32_UP32X9__NEON_MUL16, input_offset) { in TEST() argument
2990 TEST(QU8_DWCONV_MINMAX_FP32_UP32X9__NEONV8_MUL16, input_offset) { in TEST() argument
3204 TEST(QU8_DWCONV_MINMAX_FP32_UP32X25__NEON_MUL16, input_offset) { in TEST() argument
3418 TEST(QU8_DWCONV_MINMAX_FP32_UP32X25__NEONV8_MUL16, input_offset) { in TEST() argument
3632 TEST(QU8_DWCONV_MINMAX_FP32_UP8X9__SSE2_MUL16, input_offset) { in TEST() argument
3846 TEST(QU8_DWCONV_MINMAX_FP32_UP8X9__SSE41_MUL16, input_offset) { in TEST() argument
4060 TEST(QU8_DWCONV_MINMAX_FP32_UP8X9__SSE41_MUL32, input_offset) { in TEST() argument
4274 TEST(QU8_DWCONV_MINMAX_FP32_UP8X25__SSE2_MUL16, input_offset) { in TEST() argument
4488 TEST(QU8_DWCONV_MINMAX_FP32_UP8X25__SSE41_MUL16, input_offset) { in TEST() argument
4702 TEST(QU8_DWCONV_MINMAX_FP32_UP8X25__SSE41_MUL32, input_offset) { in TEST() argument
4916 TEST(QU8_DWCONV_MINMAX_FP32_UP16X9__SSE2_MUL16, input_offset) { in TEST() argument
5130 TEST(QU8_DWCONV_MINMAX_FP32_UP16X9__SSE41_MUL16, input_offset) { in TEST() argument
5344 TEST(QU8_DWCONV_MINMAX_FP32_UP16X9__SSE41_MUL32, input_offset) { in TEST() argument
5558 TEST(QU8_DWCONV_MINMAX_FP32_UP16X25__SSE2_MUL16, input_offset) { in TEST() argument
5772 TEST(QU8_DWCONV_MINMAX_FP32_UP16X25__SSE41_MUL16, input_offset) { in TEST() argument
5986 TEST(QU8_DWCONV_MINMAX_FP32_UP16X25__SSE41_MUL32, input_offset) { in TEST() argument
6200 TEST(QU8_DWCONV_MINMAX_FP32_UP8X9__AVX_MUL16, input_offset) { in TEST() argument
6414 TEST(QU8_DWCONV_MINMAX_FP32_UP8X9__AVX_MUL32, input_offset) { in TEST() argument
6628 TEST(QU8_DWCONV_MINMAX_FP32_UP8X9__AVX2_MUL32, input_offset) { in TEST() argument
6842 TEST(QU8_DWCONV_MINMAX_FP32_UP8X9__XOP_MUL32, input_offset) { in TEST() argument
7056 TEST(QU8_DWCONV_MINMAX_FP32_UP8X25__AVX_MUL16, input_offset) { in TEST() argument
7270 TEST(QU8_DWCONV_MINMAX_FP32_UP8X25__AVX_MUL32, input_offset) { in TEST() argument
7484 TEST(QU8_DWCONV_MINMAX_FP32_UP8X25__AVX2_MUL32, input_offset) { in TEST() argument
7698 TEST(QU8_DWCONV_MINMAX_FP32_UP8X25__XOP_MUL32, input_offset) { in TEST() argument
7912 TEST(QU8_DWCONV_MINMAX_FP32_UP16X9__AVX_MUL16, input_offset) { in TEST() argument
8126 TEST(QU8_DWCONV_MINMAX_FP32_UP16X9__AVX_MUL32, input_offset) { in TEST() argument
8340 TEST(QU8_DWCONV_MINMAX_FP32_UP16X9__AVX2_MUL32, input_offset) { in TEST() argument
8554 TEST(QU8_DWCONV_MINMAX_FP32_UP16X9__XOP_MUL32, input_offset) { in TEST() argument
8768 TEST(QU8_DWCONV_MINMAX_FP32_UP16X25__AVX_MUL16, input_offset) { in TEST() argument
8982 TEST(QU8_DWCONV_MINMAX_FP32_UP16X25__AVX_MUL32, input_offset) { in TEST() argument
9196 TEST(QU8_DWCONV_MINMAX_FP32_UP16X25__AVX2_MUL32, input_offset) { in TEST() argument
9410 TEST(QU8_DWCONV_MINMAX_FP32_UP16X25__XOP_MUL32, input_offset) { in TEST() argument
9624 TEST(QU8_DWCONV_MINMAX_FP32_UP32X9__AVX2_MUL32, input_offset) { in TEST() argument
9838 TEST(QU8_DWCONV_MINMAX_FP32_UP32X25__AVX2_MUL32, input_offset) { in TEST() argument
10052 TEST(QU8_DWCONV_MINMAX_FP32_UP16X9__AVX512SKX_MUL32, input_offset) { in TEST() argument
10266 TEST(QU8_DWCONV_MINMAX_FP32_UP16X25__AVX512SKX_MUL32, input_offset) { in TEST() argument
10480 TEST(QU8_DWCONV_MINMAX_FP32_UP32X9__AVX512SKX_MUL32, input_offset) { in TEST() argument
10694 TEST(QU8_DWCONV_MINMAX_FP32_UP32X25__AVX512SKX_MUL32, input_offset) { in TEST() argument
10893 TEST(QU8_DWCONV_MINMAX_FP32_UP8X9__WASMSIMD_MUL16, input_offset) { in TEST() argument
11090 TEST(QU8_DWCONV_MINMAX_FP32_UP8X25__WASMSIMD_MUL16, input_offset) { in TEST() argument
11287 TEST(QU8_DWCONV_MINMAX_FP32_UP16X9__WASMSIMD_MUL16, input_offset) { in TEST() argument
11484 TEST(QU8_DWCONV_MINMAX_FP32_UP16X25__WASMSIMD_MUL16, input_offset) { in TEST() argument
11681 TEST(QU8_DWCONV_MINMAX_FP32_UP24X9__WASMSIMD_MUL16, input_offset) { in TEST() argument
11878 TEST(QU8_DWCONV_MINMAX_FP32_UP24X25__WASMSIMD_MUL16, input_offset) { in TEST() argument
12033 TEST(QU8_DWCONV_MINMAX_FP32_UP1X9__WASM_FMAGIC, input_offset) { in TEST() argument
12188 TEST(QU8_DWCONV_MINMAX_FP32_UP1X25__WASM_FMAGIC, input_offset) { in TEST() argument
12385 TEST(QU8_DWCONV_MINMAX_FP32_UP2X9__WASM_FMAGIC, input_offset) { in TEST() argument
12582 TEST(QU8_DWCONV_MINMAX_FP32_UP2X25__WASM_FMAGIC, input_offset) { in TEST() argument
12779 TEST(QU8_DWCONV_MINMAX_FP32_UP4X9__WASM_FMAGIC, input_offset) { in TEST() argument
12976 TEST(QU8_DWCONV_MINMAX_FP32_UP4X25__WASM_FMAGIC, input_offset) { in TEST() argument
13130 TEST(QU8_DWCONV_MINMAX_FP32_UP1X9__SCALAR_FMAGIC, input_offset) { in TEST() argument
13282 TEST(QU8_DWCONV_MINMAX_FP32_UP1X9__SCALAR_IMAGIC, input_offset) { in TEST() argument
13434 TEST(QU8_DWCONV_MINMAX_FP32_UP1X9__SCALAR_LRINTF, input_offset) { in TEST() argument
13586 TEST(QU8_DWCONV_MINMAX_FP32_UP1X25__SCALAR_FMAGIC, input_offset) { in TEST() argument
13738 TEST(QU8_DWCONV_MINMAX_FP32_UP1X25__SCALAR_IMAGIC, input_offset) { in TEST() argument
13890 TEST(QU8_DWCONV_MINMAX_FP32_UP1X25__SCALAR_LRINTF, input_offset) { in TEST() argument
14084 TEST(QU8_DWCONV_MINMAX_FP32_UP2X9__SCALAR_FMAGIC, input_offset) { in TEST() argument
14278 TEST(QU8_DWCONV_MINMAX_FP32_UP2X9__SCALAR_IMAGIC, input_offset) { in TEST() argument
14472 TEST(QU8_DWCONV_MINMAX_FP32_UP2X9__SCALAR_LRINTF, input_offset) { in TEST() argument
14666 TEST(QU8_DWCONV_MINMAX_FP32_UP2X25__SCALAR_FMAGIC, input_offset) { in TEST() argument
14860 TEST(QU8_DWCONV_MINMAX_FP32_UP2X25__SCALAR_IMAGIC, input_offset) { in TEST() argument
15054 TEST(QU8_DWCONV_MINMAX_FP32_UP2X25__SCALAR_LRINTF, input_offset) { in TEST() argument
15248 TEST(QU8_DWCONV_MINMAX_FP32_UP4X9__SCALAR_FMAGIC, input_offset) { in TEST() argument
15442 TEST(QU8_DWCONV_MINMAX_FP32_UP4X9__SCALAR_IMAGIC, input_offset) { in TEST() argument
15636 TEST(QU8_DWCONV_MINMAX_FP32_UP4X9__SCALAR_LRINTF, input_offset) { in TEST() argument
15830 TEST(QU8_DWCONV_MINMAX_FP32_UP4X25__SCALAR_FMAGIC, input_offset) { in TEST() argument
16024 TEST(QU8_DWCONV_MINMAX_FP32_UP4X25__SCALAR_IMAGIC, input_offset) { in TEST() argument
16218 TEST(QU8_DWCONV_MINMAX_FP32_UP4X25__SCALAR_LRINTF, input_offset) { in TEST() argument