Lines Matching defs:a_offset
414 TEST(QS8_IGEMM_MINMAX_FP32_1X1C4__ARMSIMD32, a_offset) { in TEST() argument
882 TEST(QS8_IGEMM_MINMAX_FP32_2X1C4__ARMSIMD32, a_offset) { in TEST() argument
1350 TEST(QS8_IGEMM_MINMAX_FP32_1X8C2__NEON_MLAL_DUP, a_offset) { in TEST() argument
1818 TEST(QS8_IGEMM_MINMAX_FP32_1X8C2__NEON_MLAL_LD2R, a_offset) { in TEST() argument
2286 TEST(QS8_IGEMM_MINMAX_FP32_1X8C2__NEON_MLAL_LD4R, a_offset) { in TEST() argument
2754 TEST(QS8_IGEMM_MINMAX_FP32_1X8C2__NEONV8_MLAL_LD2R, a_offset) { in TEST() argument
3222 TEST(QS8_IGEMM_MINMAX_FP32_1X8C2__NEONV8_MLAL_LD4R, a_offset) { in TEST() argument
3690 TEST(QS8_IGEMM_MINMAX_FP32_1X8C2S4__NEON_MLAL, a_offset) { in TEST() argument
4158 TEST(QS8_IGEMM_MINMAX_FP32_1X8C2S4__NEONV8_MLAL, a_offset) { in TEST() argument
4626 TEST(QS8_IGEMM_MINMAX_FP32_1X8C4__NEON_MLAL_DUP, a_offset) { in TEST() argument
5094 TEST(QS8_IGEMM_MINMAX_FP32_1X8C4__NEON_MLAL_LD2R, a_offset) { in TEST() argument
5562 TEST(QS8_IGEMM_MINMAX_FP32_1X8C4__NEONV8_MLAL_DUP, a_offset) { in TEST() argument
6030 TEST(QS8_IGEMM_MINMAX_FP32_1X8C4__NEONV8_MLAL_LD1R, a_offset) { in TEST() argument
6498 TEST(QS8_IGEMM_MINMAX_FP32_1X8C4S2__NEON_MLAL, a_offset) { in TEST() argument
6966 TEST(QS8_IGEMM_MINMAX_FP32_1X8C4S2__NEONV8_MLAL, a_offset) { in TEST() argument
7434 TEST(QS8_IGEMM_MINMAX_FP32_2X8C2__NEON_MLAL_DUP, a_offset) { in TEST() argument
7902 TEST(QS8_IGEMM_MINMAX_FP32_2X8C2__NEON_MLAL_LD1R, a_offset) { in TEST() argument
8370 TEST(QS8_IGEMM_MINMAX_FP32_2X8C2__NEONV8_MLAL_LD1R, a_offset) { in TEST() argument
8838 TEST(QS8_IGEMM_MINMAX_FP32_2X8C2S4__NEON_MLAL, a_offset) { in TEST() argument
9306 TEST(QS8_IGEMM_MINMAX_FP32_2X8C2S4__NEONV8_MLAL, a_offset) { in TEST() argument
9774 TEST(QS8_IGEMM_MINMAX_FP32_2X8C4__NEON_MLAL_DUP, a_offset) { in TEST() argument
10242 TEST(QS8_IGEMM_MINMAX_FP32_2X8C4__NEON_MLAL_LD1R, a_offset) { in TEST() argument
10710 TEST(QS8_IGEMM_MINMAX_FP32_2X8C4__NEONV8_MLAL_DUP, a_offset) { in TEST() argument
11178 TEST(QS8_IGEMM_MINMAX_FP32_2X8C4__NEONV8_MLAL_LD2R, a_offset) { in TEST() argument
11646 TEST(QS8_IGEMM_MINMAX_FP32_2X8C4S2__NEON_MLAL, a_offset) { in TEST() argument
12114 TEST(QS8_IGEMM_MINMAX_FP32_2X8C4S2__NEONV8_MLAL, a_offset) { in TEST() argument
12582 TEST(QS8_IGEMM_MINMAX_FP32_1X8C8__AARCH64_NEON_MLAL_CORTEX_A53, a_offset) { in TEST() argument
13050 TEST(QS8_IGEMM_MINMAX_FP32_2X8C16__AARCH64_NEON_MLAL, a_offset) { in TEST() argument
13518 TEST(QS8_IGEMM_MINMAX_FP32_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, a_offset) { in TEST() argument
13986 TEST(QS8_IGEMM_MINMAX_FP32_4X16C4__AARCH64_NEONDOT_CORTEX_A55, a_offset) { in TEST() argument
14454 TEST(QS8_IGEMM_MINMAX_FP32_1X8C4__NEONDOT, a_offset) { in TEST() argument
14922 TEST(QS8_IGEMM_MINMAX_FP32_1X8C8__NEONV8_MLAL, a_offset) { in TEST() argument
15390 TEST(QS8_IGEMM_MINMAX_FP32_2X8C8__NEONV8_MLAL, a_offset) { in TEST() argument
15858 TEST(QS8_IGEMM_MINMAX_FP32_4X16__NEON_MLAL_LANE, a_offset) { in TEST() argument
16326 TEST(QS8_IGEMM_MINMAX_FP32_3X4C2__SSE2_LD64, a_offset) { in TEST() argument
16794 TEST(QS8_IGEMM_MINMAX_FP32_3X4C2__SSE41_LD64, a_offset) { in TEST() argument
17262 TEST(QS8_IGEMM_MINMAX_FP32_2X4C2__AVX_LD64, a_offset) { in TEST() argument
17730 TEST(QS8_IGEMM_MINMAX_FP32_2X4C2__XOP_LD64, a_offset) { in TEST() argument
18198 TEST(QS8_IGEMM_MINMAX_FP32_3X4C2__AVX_LD64, a_offset) { in TEST() argument
18666 TEST(QS8_IGEMM_MINMAX_FP32_3X4C2__XOP_LD64, a_offset) { in TEST() argument
19134 TEST(QS8_IGEMM_MINMAX_FP32_4X4C2__AVX_LD64, a_offset) { in TEST() argument
19602 TEST(QS8_IGEMM_MINMAX_FP32_4X4C2__XOP_LD64, a_offset) { in TEST() argument
20070 TEST(QS8_IGEMM_MINMAX_FP32_1X4C2__SSE2_LD128, a_offset) { in TEST() argument
20538 TEST(QS8_IGEMM_MINMAX_FP32_1X4C2__SSE41_LD128, a_offset) { in TEST() argument
21006 TEST(QS8_IGEMM_MINMAX_FP32_2X4C2__SSE2_LD128, a_offset) { in TEST() argument
21474 TEST(QS8_IGEMM_MINMAX_FP32_2X4C2__SSE41_LD128, a_offset) { in TEST() argument
21942 TEST(QS8_IGEMM_MINMAX_FP32_4X4C2__SSE2_LD128, a_offset) { in TEST() argument
22410 TEST(QS8_IGEMM_MINMAX_FP32_1X4C2__XOP_LD128, a_offset) { in TEST() argument
22878 TEST(QS8_IGEMM_MINMAX_FP32_2X4C2__XOP_LD128, a_offset) { in TEST() argument
23346 TEST(QS8_IGEMM_MINMAX_FP32_3X4C2__AVX_LD128, a_offset) { in TEST() argument
23814 TEST(QS8_IGEMM_MINMAX_FP32_4X4C2__XOP_LD128, a_offset) { in TEST() argument
24282 TEST(QS8_IGEMM_MINMAX_FP32_1X4C2S4__SSE2_LD64, a_offset) { in TEST() argument
24750 TEST(QS8_IGEMM_MINMAX_FP32_2X4C2S4__SSE2_LD64, a_offset) { in TEST() argument
25218 TEST(QS8_IGEMM_MINMAX_FP32_2X4C2S4__SSE41_LD64, a_offset) { in TEST() argument
25686 TEST(QS8_IGEMM_MINMAX_FP32_3X4C2S4__SSE41_LD64, a_offset) { in TEST() argument
26154 TEST(QS8_IGEMM_MINMAX_FP32_3X4C2S4__AVX_LD64, a_offset) { in TEST() argument
26622 TEST(QS8_IGEMM_MINMAX_FP32_3X4C2S4__XOP_LD64, a_offset) { in TEST() argument
27090 TEST(QS8_IGEMM_MINMAX_FP32_1X4C2S4__SSE2_LD128, a_offset) { in TEST() argument
27558 TEST(QS8_IGEMM_MINMAX_FP32_4X4C2S4__SSE2_LD128, a_offset) { in TEST() argument
28026 TEST(QS8_IGEMM_MINMAX_FP32_4X4C2S4__SSE41_LD128, a_offset) { in TEST() argument
28494 TEST(QS8_IGEMM_MINMAX_FP32_1X4C2S4__AVX_LD128, a_offset) { in TEST() argument
28962 TEST(QS8_IGEMM_MINMAX_FP32_2X4C2S4__AVX_LD128, a_offset) { in TEST() argument
29430 TEST(QS8_IGEMM_MINMAX_FP32_3X4C2S4__XOP_LD128, a_offset) { in TEST() argument
29898 TEST(QS8_IGEMM_MINMAX_FP32_4X4C2S4__XOP_LD128, a_offset) { in TEST() argument
30366 TEST(QS8_IGEMM_MINMAX_FP32_1X4C8__SSE2_LD64, a_offset) { in TEST() argument
30834 TEST(QS8_IGEMM_MINMAX_FP32_2X4C8__SSE2_LD64, a_offset) { in TEST() argument
31302 TEST(QS8_IGEMM_MINMAX_FP32_3X4C8__SSSE3_LD64, a_offset) { in TEST() argument
31770 TEST(QS8_IGEMM_MINMAX_FP32_3X4C8__SSE41_LD64, a_offset) { in TEST() argument
32238 TEST(QS8_IGEMM_MINMAX_FP32_2X4C8__AVX_LD64, a_offset) { in TEST() argument
32706 TEST(QS8_IGEMM_MINMAX_FP32_2X4C8__XOP_LD64, a_offset) { in TEST() argument
33174 TEST(QS8_IGEMM_MINMAX_FP32_3X4C8__AVX_LD64, a_offset) { in TEST() argument
33642 TEST(QS8_IGEMM_MINMAX_FP32_3X4C8__XOP_LD64, a_offset) { in TEST() argument
34110 TEST(QS8_IGEMM_MINMAX_FP32_1X4C8__SSE2_LD128, a_offset) { in TEST() argument
34578 TEST(QS8_IGEMM_MINMAX_FP32_2X4C8__SSE2_LD128, a_offset) { in TEST() argument
35046 TEST(QS8_IGEMM_MINMAX_FP32_3X4C8__SSSE3_LD128, a_offset) { in TEST() argument
35514 TEST(QS8_IGEMM_MINMAX_FP32_3X4C8__SSE41_LD128, a_offset) { in TEST() argument
35982 TEST(QS8_IGEMM_MINMAX_FP32_1X4C8__AVX_LD128, a_offset) { in TEST() argument
36450 TEST(QS8_IGEMM_MINMAX_FP32_2X4C8__AVX_LD128, a_offset) { in TEST() argument
36918 TEST(QS8_IGEMM_MINMAX_FP32_3X4C8__XOP_LD128, a_offset) { in TEST() argument
37386 TEST(QS8_IGEMM_MINMAX_FP32_1X8C8__AVX2, a_offset) { in TEST() argument
37854 TEST(QS8_IGEMM_MINMAX_FP32_3X16C8__AVX512SKX, a_offset) { in TEST() argument
38300 TEST(QS8_IGEMM_MINMAX_FP32_1X4C2__WASMSIMD_DOT16X2_LD64, a_offset) { in TEST() argument
38741 TEST(QS8_IGEMM_MINMAX_FP32_1X4C2__WASMSIMD_DOT16X2_LD128, a_offset) { in TEST() argument
39182 TEST(QS8_IGEMM_MINMAX_FP32_1X4C2S4__WASMSIMD_DOT16X2_LD128, a_offset) { in TEST() argument
39623 TEST(QS8_IGEMM_MINMAX_FP32_1X4C8__WASMSIMD_DOT16X2_LD128, a_offset) { in TEST() argument
40064 TEST(QS8_IGEMM_MINMAX_FP32_2X4C2__WASMSIMD_DOT16X2_LD128, a_offset) { in TEST() argument
40505 TEST(QS8_IGEMM_MINMAX_FP32_2X4C8__WASMSIMD_DOT16X2_LD64, a_offset) { in TEST() argument
40946 TEST(QS8_IGEMM_MINMAX_FP32_2X4C8__WASMSIMD_DOT16X2_LD128, a_offset) { in TEST() argument
41387 TEST(QS8_IGEMM_MINMAX_FP32_3X4C2__WASMSIMD_DOT16X2_LD64, a_offset) { in TEST() argument
41828 TEST(QS8_IGEMM_MINMAX_FP32_3X4C2__WASMSIMD_DOT16X2_LD128, a_offset) { in TEST() argument
42269 TEST(QS8_IGEMM_MINMAX_FP32_3X4C2S4__WASMSIMD_DOT16X2_LD128, a_offset) { in TEST() argument
42710 TEST(QS8_IGEMM_MINMAX_FP32_3X4C8__WASMSIMD_DOT16X2_LD128, a_offset) { in TEST() argument
43151 TEST(QS8_IGEMM_MINMAX_FP32_4X4C8__WASMSIMD_DOT16X2_LD64, a_offset) { in TEST() argument
43526 TEST(QS8_IGEMM_MINMAX_FP32_1X2__WASM_FMAGIC, a_offset) { in TEST() argument
43901 TEST(QS8_IGEMM_MINMAX_FP32_1X4__WASM_FMAGIC, a_offset) { in TEST() argument
44276 TEST(QS8_IGEMM_MINMAX_FP32_2X2__WASM_FMAGIC, a_offset) { in TEST() argument
44651 TEST(QS8_IGEMM_MINMAX_FP32_2X4__WASM_FMAGIC, a_offset) { in TEST() argument
45026 TEST(QS8_IGEMM_MINMAX_FP32_4X2__WASM_FMAGIC, a_offset) { in TEST() argument
45401 TEST(QS8_IGEMM_MINMAX_FP32_4X4__WASM_FMAGIC, a_offset) { in TEST() argument
45775 TEST(QS8_IGEMM_MINMAX_FP32_1X2__SCALAR_IMAGIC, a_offset) { in TEST() argument
46148 TEST(QS8_IGEMM_MINMAX_FP32_1X4__SCALAR_IMAGIC, a_offset) { in TEST() argument
46521 TEST(QS8_IGEMM_MINMAX_FP32_2X2__SCALAR_IMAGIC, a_offset) { in TEST() argument
46894 TEST(QS8_IGEMM_MINMAX_FP32_2X4__SCALAR_IMAGIC, a_offset) { in TEST() argument
47267 TEST(QS8_IGEMM_MINMAX_FP32_3X2__SCALAR_FMAGIC, a_offset) { in TEST() argument
47640 TEST(QS8_IGEMM_MINMAX_FP32_3X2__SCALAR_LRINTF, a_offset) { in TEST() argument
48013 TEST(QS8_IGEMM_MINMAX_FP32_3X4__SCALAR_FMAGIC, a_offset) { in TEST() argument
48386 TEST(QS8_IGEMM_MINMAX_FP32_3X4__SCALAR_LRINTF, a_offset) { in TEST() argument
48759 TEST(QS8_IGEMM_MINMAX_FP32_4X2__SCALAR_FMAGIC, a_offset) { in TEST() argument
49132 TEST(QS8_IGEMM_MINMAX_FP32_4X2__SCALAR_LRINTF, a_offset) { in TEST() argument
49505 TEST(QS8_IGEMM_MINMAX_FP32_4X4__SCALAR_FMAGIC, a_offset) { in TEST() argument
49878 TEST(QS8_IGEMM_MINMAX_FP32_4X4__SCALAR_LRINTF, a_offset) { in TEST() argument