Lines Matching defs:a_offset
414 TEST(QC8_IGEMM_MINMAX_FP32_1X8__AARCH32_NEON_MLAL_LANE_PRFM_CORTEX_A7, a_offset) { in TEST() argument
882 TEST(QC8_IGEMM_MINMAX_FP32_1X8__AARCH32_NEONV8_MLAL_LANE_PRFM_CORTEX_A35, a_offset) { in TEST() argument
1350 TEST(QC8_IGEMM_MINMAX_FP32_4X8__AARCH32_NEON_MLAL_LANE_LD64, a_offset) { in TEST() argument
1818 TEST(QC8_IGEMM_MINMAX_FP32_4X8__AARCH32_NEON_MLAL_LANE_PRFM_CORTEX_A53, a_offset) { in TEST() argument
2286 TEST(QC8_IGEMM_MINMAX_FP32_4X8C4__AARCH32_NEONDOT_CORTEX_A55, a_offset) { in TEST() argument
2754 TEST(QC8_IGEMM_MINMAX_FP32_4X8C4__AARCH32_NEONDOT_LD64, a_offset) { in TEST() argument
3222 TEST(QC8_IGEMM_MINMAX_FP32_1X8C8__AARCH64_NEON_MLAL_PRFM, a_offset) { in TEST() argument
3690 TEST(QC8_IGEMM_MINMAX_FP32_2X8C8__AARCH64_NEON_MLAL, a_offset) { in TEST() argument
4158 TEST(QC8_IGEMM_MINMAX_FP32_2X8C8__AARCH64_NEON_MLAL_CORTEX_A53, a_offset) { in TEST() argument
4626 TEST(QC8_IGEMM_MINMAX_FP32_2X8C16__AARCH64_NEON_MLAL, a_offset) { in TEST() argument
5094 TEST(QC8_IGEMM_MINMAX_FP32_1X8__NEONV8_MLAL_LANE, a_offset) { in TEST() argument
5562 TEST(QC8_IGEMM_MINMAX_FP32_1X8C2__NEON_MLAL_LD2R, a_offset) { in TEST() argument
6030 TEST(QC8_IGEMM_MINMAX_FP32_1X8C2__NEON_MLAL_LD4R, a_offset) { in TEST() argument
6498 TEST(QC8_IGEMM_MINMAX_FP32_1X8C4__NEON_MLAL_LD1R, a_offset) { in TEST() argument
6966 TEST(QC8_IGEMM_MINMAX_FP32_1X8C4S2__NEONV8_MLAL, a_offset) { in TEST() argument
7434 TEST(QC8_IGEMM_MINMAX_FP32_1X8C8__NEONV8_MLAL, a_offset) { in TEST() argument
7902 TEST(QC8_IGEMM_MINMAX_FP32_1X16__NEON_MLAL_LANE, a_offset) { in TEST() argument
8370 TEST(QC8_IGEMM_MINMAX_FP32_1X16__NEONV8_MLAL_LANE_PRFM, a_offset) { in TEST() argument
8838 TEST(QC8_IGEMM_MINMAX_FP32_2X8C2__NEON_MLAL_LD2R, a_offset) { in TEST() argument
9306 TEST(QC8_IGEMM_MINMAX_FP32_2X8C2__NEON_MLAL_LD4R, a_offset) { in TEST() argument
9774 TEST(QC8_IGEMM_MINMAX_FP32_2X8C2__NEONV8_MLAL_DUP, a_offset) { in TEST() argument
10242 TEST(QC8_IGEMM_MINMAX_FP32_2X8C4__NEON_MLAL_DUP, a_offset) { in TEST() argument
10710 TEST(QC8_IGEMM_MINMAX_FP32_2X8C8__NEON_MLAL, a_offset) { in TEST() argument
11178 TEST(QC8_IGEMM_MINMAX_FP32_2X16__NEON_MLAL_LANE, a_offset) { in TEST() argument
11646 TEST(QC8_IGEMM_MINMAX_FP32_3X8__NEON_MLAL_LANE_PRFM, a_offset) { in TEST() argument
12114 TEST(QC8_IGEMM_MINMAX_FP32_3X16__NEON_MLAL_LANE, a_offset) { in TEST() argument
12582 TEST(QC8_IGEMM_MINMAX_FP32_3X16__NEON_MLAL_LANE_PRFM, a_offset) { in TEST() argument
13050 TEST(QC8_IGEMM_MINMAX_FP32_3X16__NEONV8_MLAL_LANE, a_offset) { in TEST() argument
13518 TEST(QC8_IGEMM_MINMAX_FP32_4X8__NEON_MLAL_LANE, a_offset) { in TEST() argument
13986 TEST(QC8_IGEMM_MINMAX_FP32_4X8__NEONV8_MLAL_LANE, a_offset) { in TEST() argument
14454 TEST(QC8_IGEMM_MINMAX_FP32_4X16__NEONV8_MLAL_LANE, a_offset) { in TEST() argument
14922 TEST(QC8_IGEMM_MINMAX_FP32_4X16__NEONV8_MLAL_LANE_PRFM, a_offset) { in TEST() argument
15390 TEST(QC8_IGEMM_MINMAX_FP32_4X16C4__NEONDOT, a_offset) { in TEST() argument
15858 TEST(QC8_IGEMM_MINMAX_FP32_6X8__NEON_MLAL_LANE_PRFM, a_offset) { in TEST() argument
16326 TEST(QC8_IGEMM_MINMAX_FP32_6X8__NEONV8_MLAL_LANE, a_offset) { in TEST() argument
16794 TEST(QC8_IGEMM_MINMAX_FP32_6X8C4__NEONDOT, a_offset) { in TEST() argument
17262 TEST(QC8_IGEMM_MINMAX_FP32_6X16__NEON_MLAL_LANE, a_offset) { in TEST() argument
17730 TEST(QC8_IGEMM_MINMAX_FP32_6X16C4__NEONDOT, a_offset) { in TEST() argument
18198 TEST(QC8_IGEMM_MINMAX_FP32_8X8C4__NEONDOT, a_offset) { in TEST() argument
18666 TEST(QC8_IGEMM_MINMAX_FP32_1X4C2__SSE2_LD64, a_offset) { in TEST() argument
19134 TEST(QC8_IGEMM_MINMAX_FP32_1X4C2__SSE41_LD64, a_offset) { in TEST() argument
19602 TEST(QC8_IGEMM_MINMAX_FP32_3X4C2__SSE2_LD64, a_offset) { in TEST() argument
20070 TEST(QC8_IGEMM_MINMAX_FP32_4X4C2__SSE41_LD64, a_offset) { in TEST() argument
20538 TEST(QC8_IGEMM_MINMAX_FP32_1X4C2__AVX_LD64, a_offset) { in TEST() argument
21006 TEST(QC8_IGEMM_MINMAX_FP32_3X4C2__AVX_LD64, a_offset) { in TEST() argument
21474 TEST(QC8_IGEMM_MINMAX_FP32_1X4C2__SSE2_LD128, a_offset) { in TEST() argument
21942 TEST(QC8_IGEMM_MINMAX_FP32_3X4C2__SSE2_LD128, a_offset) { in TEST() argument
22410 TEST(QC8_IGEMM_MINMAX_FP32_3X4C2__SSE41_LD128, a_offset) { in TEST() argument
22878 TEST(QC8_IGEMM_MINMAX_FP32_4X4C2__SSE2_LD128, a_offset) { in TEST() argument
23346 TEST(QC8_IGEMM_MINMAX_FP32_4X4C2__SSE41_LD128, a_offset) { in TEST() argument
23814 TEST(QC8_IGEMM_MINMAX_FP32_3X4C2__XOP_LD128, a_offset) { in TEST() argument
24282 TEST(QC8_IGEMM_MINMAX_FP32_4X4C2__AVX_LD128, a_offset) { in TEST() argument
24750 TEST(QC8_IGEMM_MINMAX_FP32_4X4C2__XOP_LD128, a_offset) { in TEST() argument
25218 TEST(QC8_IGEMM_MINMAX_FP32_1X4C2S4__SSE41_LD64, a_offset) { in TEST() argument
25686 TEST(QC8_IGEMM_MINMAX_FP32_3X4C2S4__SSE2_LD64, a_offset) { in TEST() argument
26154 TEST(QC8_IGEMM_MINMAX_FP32_3X4C2S4__XOP_LD64, a_offset) { in TEST() argument
26622 TEST(QC8_IGEMM_MINMAX_FP32_2X4C2S4__SSE41_LD128, a_offset) { in TEST() argument
27090 TEST(QC8_IGEMM_MINMAX_FP32_4X4C2S4__SSE41_LD128, a_offset) { in TEST() argument
27558 TEST(QC8_IGEMM_MINMAX_FP32_1X4C2S4__AVX_LD128, a_offset) { in TEST() argument
28026 TEST(QC8_IGEMM_MINMAX_FP32_2X4C2S4__XOP_LD128, a_offset) { in TEST() argument
28494 TEST(QC8_IGEMM_MINMAX_FP32_3X4C2S4__AVX_LD128, a_offset) { in TEST() argument
28962 TEST(QC8_IGEMM_MINMAX_FP32_2X4C8__SSE2_LD64, a_offset) { in TEST() argument
29430 TEST(QC8_IGEMM_MINMAX_FP32_2X4C8__SSE41_LD64, a_offset) { in TEST() argument
29898 TEST(QC8_IGEMM_MINMAX_FP32_3X4C8__SSE2_LD64, a_offset) { in TEST() argument
30366 TEST(QC8_IGEMM_MINMAX_FP32_3X4C8__SSE41_LD64, a_offset) { in TEST() argument
30834 TEST(QC8_IGEMM_MINMAX_FP32_3X4C8__XOP_LD64, a_offset) { in TEST() argument
31302 TEST(QC8_IGEMM_MINMAX_FP32_2X4C8__SSE2_LD128, a_offset) { in TEST() argument
31770 TEST(QC8_IGEMM_MINMAX_FP32_3X4C8__SSE41_LD128, a_offset) { in TEST() argument
32238 TEST(QC8_IGEMM_MINMAX_FP32_1X8C8__AVX2, a_offset) { in TEST() argument
32706 TEST(QC8_IGEMM_MINMAX_FP32_3X8C8__AVX2, a_offset) { in TEST() argument
33174 TEST(QC8_IGEMM_MINMAX_FP32_2X16C8__AVX512SKX, a_offset) { in TEST() argument
33620 TEST(QC8_IGEMM_MINMAX_FP32_1X4C8__WASMSIMD_DOT16X2_LD64, a_offset) { in TEST() argument
34061 TEST(QC8_IGEMM_MINMAX_FP32_2X4C2__WASMSIMD_DOT16X2_LD128, a_offset) { in TEST() argument
34502 TEST(QC8_IGEMM_MINMAX_FP32_3X4C2S4__WASMSIMD_DOT16X2_LD128, a_offset) { in TEST() argument
34943 TEST(QC8_IGEMM_MINMAX_FP32_4X4C2__WASMSIMD_DOT16X2_LD64, a_offset) { in TEST() argument
35318 TEST(QC8_IGEMM_MINMAX_FP32_4X2__WASM_FMAGIC, a_offset) { in TEST() argument
35692 TEST(QC8_IGEMM_MINMAX_FP32_1X2__SCALAR_LRINTF, a_offset) { in TEST() argument
36065 TEST(QC8_IGEMM_MINMAX_FP32_1X4__SCALAR_IMAGIC, a_offset) { in TEST() argument
36438 TEST(QC8_IGEMM_MINMAX_FP32_1X4__SCALAR_LRINTF, a_offset) { in TEST() argument
36811 TEST(QC8_IGEMM_MINMAX_FP32_2X2__SCALAR_FMAGIC, a_offset) { in TEST() argument
37184 TEST(QC8_IGEMM_MINMAX_FP32_2X4__SCALAR_IMAGIC, a_offset) { in TEST() argument
37557 TEST(QC8_IGEMM_MINMAX_FP32_3X2__SCALAR_FMAGIC, a_offset) { in TEST() argument
37930 TEST(QC8_IGEMM_MINMAX_FP32_3X2__SCALAR_IMAGIC, a_offset) { in TEST() argument
38303 TEST(QC8_IGEMM_MINMAX_FP32_3X2__SCALAR_LRINTF, a_offset) { in TEST() argument
38676 TEST(QC8_IGEMM_MINMAX_FP32_4X2__SCALAR_LRINTF, a_offset) { in TEST() argument
39049 TEST(QC8_IGEMM_MINMAX_FP32_4X4__SCALAR_FMAGIC, a_offset) { in TEST() argument
39511 TEST(GENERATE_QC8_IGEMM_FP32_4X8__AARCH32_NEONV8_MLAL_LANE_LD64, a_offset) { in TEST() argument
39979 TEST(GENERATE_QC8_IGEMM_FP32_4X8C4__AARCH32_NEONDOT_LD64, a_offset) { in TEST() argument