326   TEST(F32_IGEMM_RELU_1X8__WASMSIMD_LOADSPLAT, a_offset) {  in TEST()  argument
741   TEST(F32_IGEMM_RELU_3X8__WASMSIMD_SPLAT, a_offset) {  in TEST()  argument
1156   TEST(F32_IGEMM_RELU_3X8S4__WASMSIMD, a_offset) {  in TEST()  argument
1571   TEST(F32_IGEMM_RELU_4X2C4__WASMSIMD, a_offset) {  in TEST()  argument
1986   TEST(F32_IGEMM_RELU_4X8S4__WASMSIMD, a_offset) {  in TEST()  argument
2401   TEST(F32_IGEMM_RELU_5X8S4__WASMSIMD, a_offset) {  in TEST()  argument
2750   TEST(F32_IGEMM_RELU_6X8__WASMSIMD_LOADSPLAT, a_offset) {  in TEST()  argument
3165   TEST(F32_IGEMM_RELU_6X8__WASMSIMD_SPLAT, a_offset) {  in TEST()  argument
3514   TEST(F32_IGEMM_RELU_1X8__WASMRELAXEDSIMD_FMA_LOADSPLAT, a_offset) {  in TEST()  argument
3863   TEST(F32_IGEMM_RELU_3X8__WASMRELAXEDSIMD_FMA_LOADSPLAT, a_offset) {  in TEST()  argument
4278   TEST(F32_IGEMM_RELU_3X8S4__WASMRELAXEDSIMD_FMA, a_offset) {  in TEST()  argument
4627   TEST(F32_IGEMM_RELU_4X8__WASMRELAXEDSIMD_FMA_LOADSPLAT, a_offset) {  in TEST()  argument
5042   TEST(F32_IGEMM_RELU_4X8S4__WASMRELAXEDSIMD_FMA, a_offset) {  in TEST()  argument
5391   TEST(F32_IGEMM_RELU_5X8__WASMRELAXEDSIMD_FMA_LOADSPLAT, a_offset) {  in TEST()  argument
5740   TEST(F32_IGEMM_RELU_6X8__WASMRELAXEDSIMD_FMA_LOADSPLAT, a_offset) {  in TEST()  argument
6089   TEST(F32_IGEMM_RELU_2X4__WASM, a_offset) {  in TEST()  argument
6438   TEST(F32_IGEMM_RELU_4X2__WASM, a_offset) {  in TEST()  argument
6787   TEST(F32_IGEMM_RELU_4X4__WASM, a_offset) {  in TEST()  argument
7135 TEST(F32_IGEMM_RELU_1X4__SCALAR, a_offset) {  in TEST()  argument
7482 TEST(F32_IGEMM_RELU_4X2__SCALAR, a_offset) {  in TEST()  argument
7829 TEST(F32_IGEMM_RELU_4X4__SCALAR, a_offset) {  in TEST()  argument