Lines Matching defs:a_offset
414 TEST(F32_IGEMM_MINMAX_4X8__AARCH32_NEON_CORTEX_A7, a_offset) { in TEST() argument
913 TEST(F32_IGEMM_MINMAX_4X8__AARCH32_NEON_CORTEX_A55, a_offset) { in TEST() argument
1412 TEST(F32_IGEMM_MINMAX_4X8__AARCH32_NEON_CORTEX_A75, a_offset) { in TEST() argument
1911 TEST(F32_IGEMM_MINMAX_4X8__AARCH32_NEON_PRFM_CORTEX_A75, a_offset) { in TEST() argument
2410 TEST(F32_IGEMM_MINMAX_1X8__AARCH64_NEONFMA_CORTEX_A75, a_offset) { in TEST() argument
2909 TEST(F32_IGEMM_MINMAX_1X8__AARCH64_NEONFMA_PRFM_CORTEX_A53, a_offset) { in TEST() argument
3377 TEST(F32_IGEMM_MINMAX_4X2__AARCH64_NEONFMA_LD64, a_offset) { in TEST() argument
3876 TEST(F32_IGEMM_MINMAX_4X2__AARCH64_NEONFMA_PRFM_CORTEX_A75, a_offset) { in TEST() argument
4375 TEST(F32_IGEMM_MINMAX_4X8__AARCH64_NEONFMA_CORTEX_A53, a_offset) { in TEST() argument
4874 TEST(F32_IGEMM_MINMAX_4X8__AARCH64_NEONFMA_PRFM_CORTEX_A53, a_offset) { in TEST() argument
5373 TEST(F32_IGEMM_MINMAX_5X8__AARCH64_NEONFMA_CORTEX_A75, a_offset) { in TEST() argument
5872 TEST(F32_IGEMM_MINMAX_5X8__AARCH64_NEONFMA_PRFM_CORTEX_A75, a_offset) { in TEST() argument
6371 TEST(F32_IGEMM_MINMAX_6X8__AARCH64_NEONFMA_CORTEX_A53, a_offset) { in TEST() argument
6870 TEST(F32_IGEMM_MINMAX_6X8__AARCH64_NEONFMA_CORTEX_A73, a_offset) { in TEST() argument
7338 TEST(F32_IGEMM_MINMAX_6X8__AARCH64_NEONFMA_LD64, a_offset) { in TEST() argument
7806 TEST(F32_IGEMM_MINMAX_6X8__AARCH64_NEONFMA_LD128, a_offset) { in TEST() argument
8305 TEST(F32_IGEMM_MINMAX_6X8__AARCH64_NEONFMA_PRFM_CORTEX_A75, a_offset) { in TEST() argument
8773 TEST(F32_IGEMM_MINMAX_1X8__NEON_DUP_LD64, a_offset) { in TEST() argument
9241 TEST(F32_IGEMM_MINMAX_1X8__NEONFMA_DUP_LD64, a_offset) { in TEST() argument
9709 TEST(F32_IGEMM_MINMAX_1X8S4__NEONFMA, a_offset) { in TEST() argument
10177 TEST(F32_IGEMM_MINMAX_4X2__NEON_LANE_LD64, a_offset) { in TEST() argument
10645 TEST(F32_IGEMM_MINMAX_4X4__NEON_LANE_LD64, a_offset) { in TEST() argument
11113 TEST(F32_IGEMM_MINMAX_4X4__NEONFMA_LANE_LD64, a_offset) { in TEST() argument
11581 TEST(F32_IGEMM_MINMAX_6X8__NEON_DUP_LD64, a_offset) { in TEST() argument
12049 TEST(F32_IGEMM_MINMAX_6X8__NEON_DUP_LD128, a_offset) { in TEST() argument
12517 TEST(F32_IGEMM_MINMAX_6X8__NEON_LANE_LD64, a_offset) { in TEST() argument
12985 TEST(F32_IGEMM_MINMAX_6X8__NEONFMA_DUP_LD64, a_offset) { in TEST() argument
13453 TEST(F32_IGEMM_MINMAX_6X8__NEONFMA_LANE_LD128, a_offset) { in TEST() argument
13921 TEST(F32_IGEMM_MINMAX_6X8S4__NEON, a_offset) { in TEST() argument
14389 TEST(F32_IGEMM_MINMAX_6X8S4__NEONFMA, a_offset) { in TEST() argument
14857 TEST(F32_IGEMM_MINMAX_8X8S4__NEON, a_offset) { in TEST() argument
15325 TEST(F32_IGEMM_MINMAX_8X8S4__NEONFMA, a_offset) { in TEST() argument
15793 TEST(F32_IGEMM_MINMAX_1X8__SSE2_DUP, a_offset) { in TEST() argument
16261 TEST(F32_IGEMM_MINMAX_3X8__SSE_DUP, a_offset) { in TEST() argument
16659 TEST(F32_IGEMM_MINMAX_3X8__SSE_LOAD1, a_offset) { in TEST() argument
17127 TEST(F32_IGEMM_MINMAX_3X8S4__SSE, a_offset) { in TEST() argument
17525 TEST(F32_IGEMM_MINMAX_4X8__SSE_LOAD1, a_offset) { in TEST() argument
17993 TEST(F32_IGEMM_MINMAX_5X8__SSE_DUP, a_offset) { in TEST() argument
18391 TEST(F32_IGEMM_MINMAX_5X8__SSE_LOAD1, a_offset) { in TEST() argument
18859 TEST(F32_IGEMM_MINMAX_5X8__SSE2_DUP, a_offset) { in TEST() argument
19257 TEST(F32_IGEMM_MINMAX_1X8__AVX_BROADCAST, a_offset) { in TEST() argument
19655 TEST(F32_IGEMM_MINMAX_1X16__AVX_BROADCAST, a_offset) { in TEST() argument
20053 TEST(F32_IGEMM_MINMAX_4X16__AVX_BROADCAST, a_offset) { in TEST() argument
20451 TEST(F32_IGEMM_MINMAX_5X8__AVX_BROADCAST, a_offset) { in TEST() argument
20849 TEST(F32_IGEMM_MINMAX_5X16__AVX_BROADCAST, a_offset) { in TEST() argument
21247 TEST(F32_IGEMM_MINMAX_6X8__AVX_BROADCAST, a_offset) { in TEST() argument
21645 TEST(F32_IGEMM_MINMAX_4X16__FMA3_BROADCAST, a_offset) { in TEST() argument
22043 TEST(F32_IGEMM_MINMAX_5X16__FMA3_BROADCAST, a_offset) { in TEST() argument
22441 TEST(F32_IGEMM_MINMAX_6X8__FMA3_BROADCAST, a_offset) { in TEST() argument
22839 TEST(F32_IGEMM_MINMAX_7X8__FMA3_BROADCAST, a_offset) { in TEST() argument
23237 TEST(F32_IGEMM_MINMAX_8X8__FMA3_BROADCAST, a_offset) { in TEST() argument
23635 TEST(F32_IGEMM_MINMAX_4X16__AVX512F_BROADCAST, a_offset) { in TEST() argument
24033 TEST(F32_IGEMM_MINMAX_5X16__AVX512F_BROADCAST, a_offset) { in TEST() argument
24413 TEST(F32_IGEMM_MINMAX_1X8__WASMSIMD_ARM_LOADSPLAT, a_offset) { in TEST() argument
24854 TEST(F32_IGEMM_MINMAX_1X8S4__WASMSIMD_ARM, a_offset) { in TEST() argument
25295 TEST(F32_IGEMM_MINMAX_1X8S4__WASMSIMD_X86, a_offset) { in TEST() argument
25670 TEST(F32_IGEMM_MINMAX_3X8__WASMSIMD_ARM_LOADSPLAT, a_offset) { in TEST() argument
26111 TEST(F32_IGEMM_MINMAX_3X8__WASMSIMD_ARM_SPLAT, a_offset) { in TEST() argument
26552 TEST(F32_IGEMM_MINMAX_3X8__WASMSIMD_X86_SPLAT, a_offset) { in TEST() argument
26927 TEST(F32_IGEMM_MINMAX_4X8__WASMSIMD_ARM_LOADSPLAT, a_offset) { in TEST() argument
27368 TEST(F32_IGEMM_MINMAX_4X8__WASMSIMD_ARM_SPLAT, a_offset) { in TEST() argument
27809 TEST(F32_IGEMM_MINMAX_4X8__WASMSIMD_X86_SPLAT, a_offset) { in TEST() argument
28250 TEST(F32_IGEMM_MINMAX_4X8S4__WASMSIMD_ARM, a_offset) { in TEST() argument
28691 TEST(F32_IGEMM_MINMAX_4X8S4__WASMSIMD_X86, a_offset) { in TEST() argument
29132 TEST(F32_IGEMM_MINMAX_5X8__WASMSIMD_ARM_SPLAT, a_offset) { in TEST() argument
29507 TEST(F32_IGEMM_MINMAX_5X8__WASMSIMD_X86_LOADSPLAT, a_offset) { in TEST() argument
29948 TEST(F32_IGEMM_MINMAX_5X8__WASMSIMD_X86_SPLAT, a_offset) { in TEST() argument
30389 TEST(F32_IGEMM_MINMAX_5X8S4__WASMSIMD_ARM, a_offset) { in TEST() argument
30830 TEST(F32_IGEMM_MINMAX_5X8S4__WASMSIMD_X86, a_offset) { in TEST() argument
31205 TEST(F32_IGEMM_MINMAX_6X8__WASMSIMD_ARM_LOADSPLAT, a_offset) { in TEST() argument
31580 TEST(F32_IGEMM_MINMAX_1X8__WASMRELAXEDSIMD_FMA_LOADSPLAT, a_offset) { in TEST() argument
32021 TEST(F32_IGEMM_MINMAX_1X8__WASMRELAXEDSIMD_FMA_SPLAT, a_offset) { in TEST() argument
32396 TEST(F32_IGEMM_MINMAX_3X8__WASMRELAXEDSIMD_FMA_LOADSPLAT, a_offset) { in TEST() argument
32837 TEST(F32_IGEMM_MINMAX_3X8__WASMRELAXEDSIMD_FMA_SPLAT, a_offset) { in TEST() argument
33278 TEST(F32_IGEMM_MINMAX_3X8__WASMRELAXEDSIMD_SPLAT, a_offset) { in TEST() argument
33719 TEST(F32_IGEMM_MINMAX_3X8S4__WASMRELAXEDSIMD_FMA, a_offset) { in TEST() argument
34094 TEST(F32_IGEMM_MINMAX_4X8__WASMRELAXEDSIMD_FMA_LOADSPLAT, a_offset) { in TEST() argument
34535 TEST(F32_IGEMM_MINMAX_4X8__WASMRELAXEDSIMD_FMA_SPLAT, a_offset) { in TEST() argument
34976 TEST(F32_IGEMM_MINMAX_4X8__WASMRELAXEDSIMD_SPLAT, a_offset) { in TEST() argument
35417 TEST(F32_IGEMM_MINMAX_4X8S4__WASMRELAXEDSIMD_FMA, a_offset) { in TEST() argument
35792 TEST(F32_IGEMM_MINMAX_5X8__WASMRELAXEDSIMD_FMA_LOADSPLAT, a_offset) { in TEST() argument
36233 TEST(F32_IGEMM_MINMAX_5X8__WASMRELAXEDSIMD_FMA_SPLAT, a_offset) { in TEST() argument
36608 TEST(F32_IGEMM_MINMAX_6X8__WASMRELAXEDSIMD_FMA_LOADSPLAT, a_offset) { in TEST() argument
37049 TEST(F32_IGEMM_MINMAX_6X8__WASMRELAXEDSIMD_FMA_SPLAT, a_offset) { in TEST() argument
37424 TEST(F32_IGEMM_MINMAX_1X4__WASM, a_offset) { in TEST() argument
37798 TEST(F32_IGEMM_MINMAX_2X4__SCALAR, a_offset) { in TEST() argument
38260 TEST(GENERATE_F32_IGEMM_4X8__AARCH32_NEON_CORTEX_A7, a_offset) { in TEST() argument
38759 TEST(GENERATE_F32_IGEMM_4X8__AARCH32_NEON_CORTEX_A55, a_offset) { in TEST() argument
39258 TEST(GENERATE_F32_IGEMM_4X8__AARCH32_NEON_CORTEX_A75, a_offset) { in TEST() argument
39726 TEST(GENERATE_F32_IGEMM_4X8__AARCH32_NEON_LD64, a_offset) { in TEST() argument
40225 TEST(GENERATE_F32_IGEMM_UPTO6X8__AARCH64_NEONFMA_CORTEX_A75, a_offset) { in TEST() argument
40742 TEST(GENERATE_F32_IGEMM_4X8__AARCH64_NEONFMA_CORTEX_A75, a_offset) { in TEST() argument