Lines Matching defs:a_offset
445 TEST(F32_IGEMM_MINMAX_4X8__AARCH32_NEON_CORTEX_A53, a_offset) { in TEST() argument
913 TEST(F32_IGEMM_MINMAX_4X8__AARCH32_NEON_LD64, a_offset) { in TEST() argument
1412 TEST(F32_IGEMM_MINMAX_4X8__AARCH32_NEON_PRFM_CORTEX_A53, a_offset) { in TEST() argument
1911 TEST(F32_IGEMM_MINMAX_1X8__AARCH64_NEONFMA_CORTEX_A53, a_offset) { in TEST() argument
2410 TEST(F32_IGEMM_MINMAX_1X8__AARCH64_NEONFMA_PRFM_CORTEX_A75, a_offset) { in TEST() argument
2909 TEST(F32_IGEMM_MINMAX_1X12__AARCH64_NEONFMA_CORTEX_A53, a_offset) { in TEST() argument
3408 TEST(F32_IGEMM_MINMAX_4X2__AARCH64_NEONFMA_CORTEX_A75, a_offset) { in TEST() argument
3907 TEST(F32_IGEMM_MINMAX_4X8__AARCH64_NEONFMA_CORTEX_A55, a_offset) { in TEST() argument
4406 TEST(F32_IGEMM_MINMAX_4X8__AARCH64_NEONFMA_CORTEX_A75, a_offset) { in TEST() argument
4874 TEST(F32_IGEMM_MINMAX_4X8__AARCH64_NEONFMA_LD64, a_offset) { in TEST() argument
5342 TEST(F32_IGEMM_MINMAX_4X8__AARCH64_NEONFMA_LD128, a_offset) { in TEST() argument
5841 TEST(F32_IGEMM_MINMAX_4X8__AARCH64_NEONFMA_PRFM_CORTEX_A75, a_offset) { in TEST() argument
6340 TEST(F32_IGEMM_MINMAX_4X12__AARCH64_NEONFMA_CORTEX_A53, a_offset) { in TEST() argument
6839 TEST(F32_IGEMM_MINMAX_6X8__AARCH64_NEONFMA_CORTEX_A55, a_offset) { in TEST() argument
7338 TEST(F32_IGEMM_MINMAX_6X8__AARCH64_NEONFMA_CORTEX_A75, a_offset) { in TEST() argument
7837 TEST(F32_IGEMM_MINMAX_6X8__AARCH64_NEONFMA_PRFM_CORTEX_A53, a_offset) { in TEST() argument
8305 TEST(F32_IGEMM_MINMAX_1X8__NEON_LANE_LD64, a_offset) { in TEST() argument
8773 TEST(F32_IGEMM_MINMAX_1X8__NEONFMA_LANE_LD64, a_offset) { in TEST() argument
9241 TEST(F32_IGEMM_MINMAX_1X8S4__NEON, a_offset) { in TEST() argument
9709 TEST(F32_IGEMM_MINMAX_4X2__NEONFMA_LANE_LD64, a_offset) { in TEST() argument
10177 TEST(F32_IGEMM_MINMAX_4X8__NEON_DUP_LD64, a_offset) { in TEST() argument
10645 TEST(F32_IGEMM_MINMAX_4X8__NEON_DUP_LD128, a_offset) { in TEST() argument
11113 TEST(F32_IGEMM_MINMAX_4X8__NEON_LANE_LD64, a_offset) { in TEST() argument
11581 TEST(F32_IGEMM_MINMAX_4X8__NEON_LANE_LD128, a_offset) { in TEST() argument
12049 TEST(F32_IGEMM_MINMAX_4X8__NEONFMA_DUP_LD64, a_offset) { in TEST() argument
12517 TEST(F32_IGEMM_MINMAX_4X8__NEONFMA_DUP_LD128, a_offset) { in TEST() argument
12985 TEST(F32_IGEMM_MINMAX_4X8__NEONFMA_LANE_LD64, a_offset) { in TEST() argument
13453 TEST(F32_IGEMM_MINMAX_4X8__NEONFMA_LANE_LD128, a_offset) { in TEST() argument
13921 TEST(F32_IGEMM_MINMAX_4X8S4__NEON, a_offset) { in TEST() argument
14389 TEST(F32_IGEMM_MINMAX_4X8S4__NEONFMA, a_offset) { in TEST() argument
14857 TEST(F32_IGEMM_MINMAX_6X2__NEON_LANE_LD64, a_offset) { in TEST() argument
15325 TEST(F32_IGEMM_MINMAX_6X2__NEONFMA_LANE_LD64, a_offset) { in TEST() argument
15793 TEST(F32_IGEMM_MINMAX_6X8__NEON_LANE_LD128, a_offset) { in TEST() argument
16261 TEST(F32_IGEMM_MINMAX_6X8__NEONFMA_DUP_LD128, a_offset) { in TEST() argument
16729 TEST(F32_IGEMM_MINMAX_6X8__NEONFMA_LANE_LD64, a_offset) { in TEST() argument
17197 TEST(F32_IGEMM_MINMAX_1X8__SSE_DUP, a_offset) { in TEST() argument
17595 TEST(F32_IGEMM_MINMAX_1X8__SSE_LOAD1, a_offset) { in TEST() argument
18063 TEST(F32_IGEMM_MINMAX_1X8S4__SSE, a_offset) { in TEST() argument
18531 TEST(F32_IGEMM_MINMAX_3X8__SSE2_DUP, a_offset) { in TEST() argument
18999 TEST(F32_IGEMM_MINMAX_4X2C4__SSE, a_offset) { in TEST() argument
19467 TEST(F32_IGEMM_MINMAX_4X8__SSE_DUP, a_offset) { in TEST() argument
19935 TEST(F32_IGEMM_MINMAX_4X8__SSE2_DUP, a_offset) { in TEST() argument
20403 TEST(F32_IGEMM_MINMAX_4X8S4__SSE, a_offset) { in TEST() argument
20871 TEST(F32_IGEMM_MINMAX_5X8S4__SSE, a_offset) { in TEST() argument
21269 TEST(F32_IGEMM_MINMAX_3X16__AVX_BROADCAST, a_offset) { in TEST() argument
21667 TEST(F32_IGEMM_MINMAX_4X8__AVX_BROADCAST, a_offset) { in TEST() argument
22065 TEST(F32_IGEMM_MINMAX_7X8__AVX_BROADCAST, a_offset) { in TEST() argument
22463 TEST(F32_IGEMM_MINMAX_1X8__FMA3_BROADCAST, a_offset) { in TEST() argument
22861 TEST(F32_IGEMM_MINMAX_1X16__FMA3_BROADCAST, a_offset) { in TEST() argument
23329 TEST(F32_IGEMM_MINMAX_1X16S4__FMA3_BROADCAST, a_offset) { in TEST() argument
23727 TEST(F32_IGEMM_MINMAX_3X16__FMA3_BROADCAST, a_offset) { in TEST() argument
24195 TEST(F32_IGEMM_MINMAX_3X16S4__FMA3_BROADCAST, a_offset) { in TEST() argument
24593 TEST(F32_IGEMM_MINMAX_4X8__FMA3_BROADCAST, a_offset) { in TEST() argument
25061 TEST(F32_IGEMM_MINMAX_4X16S4__FMA3_BROADCAST, a_offset) { in TEST() argument
25459 TEST(F32_IGEMM_MINMAX_5X8__FMA3_BROADCAST, a_offset) { in TEST() argument
25927 TEST(F32_IGEMM_MINMAX_5X16S4__FMA3_BROADCAST, a_offset) { in TEST() argument
26325 TEST(F32_IGEMM_MINMAX_1X16__AVX512F_BROADCAST, a_offset) { in TEST() argument
26723 TEST(F32_IGEMM_MINMAX_6X16__AVX512F_BROADCAST, a_offset) { in TEST() argument
27121 TEST(F32_IGEMM_MINMAX_7X16__AVX512F_BROADCAST, a_offset) { in TEST() argument
27519 TEST(F32_IGEMM_MINMAX_8X16__AVX512F_BROADCAST, a_offset) { in TEST() argument
27965 TEST(F32_IGEMM_MINMAX_1X8__WASMSIMD_ARM_SPLAT, a_offset) { in TEST() argument
28340 TEST(F32_IGEMM_MINMAX_1X8__WASMSIMD_X86_LOADSPLAT, a_offset) { in TEST() argument
28781 TEST(F32_IGEMM_MINMAX_1X8__WASMSIMD_X86_SPLAT, a_offset) { in TEST() argument
29156 TEST(F32_IGEMM_MINMAX_3X8__WASMSIMD_X86_LOADSPLAT, a_offset) { in TEST() argument
29597 TEST(F32_IGEMM_MINMAX_3X8S4__WASMSIMD_ARM, a_offset) { in TEST() argument
30038 TEST(F32_IGEMM_MINMAX_3X8S4__WASMSIMD_X86, a_offset) { in TEST() argument
30479 TEST(F32_IGEMM_MINMAX_4X2C4__WASMSIMD_ARM, a_offset) { in TEST() argument
30920 TEST(F32_IGEMM_MINMAX_4X2C4__WASMSIMD_X86, a_offset) { in TEST() argument
31295 TEST(F32_IGEMM_MINMAX_4X8__WASMSIMD_X86_LOADSPLAT, a_offset) { in TEST() argument
31670 TEST(F32_IGEMM_MINMAX_5X8__WASMSIMD_ARM_LOADSPLAT, a_offset) { in TEST() argument
32111 TEST(F32_IGEMM_MINMAX_6X8__WASMSIMD_ARM_SPLAT, a_offset) { in TEST() argument
32486 TEST(F32_IGEMM_MINMAX_6X8__WASMSIMD_X86_LOADSPLAT, a_offset) { in TEST() argument
32927 TEST(F32_IGEMM_MINMAX_6X8__WASMSIMD_X86_SPLAT, a_offset) { in TEST() argument
33368 TEST(F32_IGEMM_MINMAX_6X8S4__WASMSIMD_ARM, a_offset) { in TEST() argument
33809 TEST(F32_IGEMM_MINMAX_6X8S4__WASMSIMD_X86, a_offset) { in TEST() argument
34184 TEST(F32_IGEMM_MINMAX_1X8__WASMRELAXEDSIMD_LOADSPLAT, a_offset) { in TEST() argument
34625 TEST(F32_IGEMM_MINMAX_1X8__WASMRELAXEDSIMD_SPLAT, a_offset) { in TEST() argument
35066 TEST(F32_IGEMM_MINMAX_1X8S4__WASMRELAXEDSIMD, a_offset) { in TEST() argument
35507 TEST(F32_IGEMM_MINMAX_1X8S4__WASMRELAXEDSIMD_FMA, a_offset) { in TEST() argument
35882 TEST(F32_IGEMM_MINMAX_3X8__WASMRELAXEDSIMD_LOADSPLAT, a_offset) { in TEST() argument
36323 TEST(F32_IGEMM_MINMAX_3X8S4__WASMRELAXEDSIMD, a_offset) { in TEST() argument
36764 TEST(F32_IGEMM_MINMAX_4X2C4__WASMRELAXEDSIMD, a_offset) { in TEST() argument
37205 TEST(F32_IGEMM_MINMAX_4X2C4__WASMRELAXEDSIMD_FMA, a_offset) { in TEST() argument
37580 TEST(F32_IGEMM_MINMAX_4X8__WASMRELAXEDSIMD_LOADSPLAT, a_offset) { in TEST() argument
38021 TEST(F32_IGEMM_MINMAX_4X8S4__WASMRELAXEDSIMD, a_offset) { in TEST() argument
38396 TEST(F32_IGEMM_MINMAX_5X8__WASMRELAXEDSIMD_LOADSPLAT, a_offset) { in TEST() argument
38837 TEST(F32_IGEMM_MINMAX_5X8__WASMRELAXEDSIMD_SPLAT, a_offset) { in TEST() argument
39278 TEST(F32_IGEMM_MINMAX_5X8S4__WASMRELAXEDSIMD, a_offset) { in TEST() argument
39719 TEST(F32_IGEMM_MINMAX_5X8S4__WASMRELAXEDSIMD_FMA, a_offset) { in TEST() argument
40094 TEST(F32_IGEMM_MINMAX_6X8__WASMRELAXEDSIMD_LOADSPLAT, a_offset) { in TEST() argument
40535 TEST(F32_IGEMM_MINMAX_6X8__WASMRELAXEDSIMD_SPLAT, a_offset) { in TEST() argument
40976 TEST(F32_IGEMM_MINMAX_6X8S4__WASMRELAXEDSIMD, a_offset) { in TEST() argument
41417 TEST(F32_IGEMM_MINMAX_6X8S4__WASMRELAXEDSIMD_FMA, a_offset) { in TEST() argument
41792 TEST(F32_IGEMM_MINMAX_2X4__WASM, a_offset) { in TEST() argument
42167 TEST(F32_IGEMM_MINMAX_4X2__WASM, a_offset) { in TEST() argument
42542 TEST(F32_IGEMM_MINMAX_4X4__WASM, a_offset) { in TEST() argument
42916 TEST(F32_IGEMM_MINMAX_1X4__SCALAR, a_offset) { in TEST() argument
43289 TEST(F32_IGEMM_MINMAX_4X2__SCALAR, a_offset) { in TEST() argument
43662 TEST(F32_IGEMM_MINMAX_4X4__SCALAR, a_offset) { in TEST() argument
44155 TEST(GENERATE_F32_IGEMM_4X8__AARCH32_NEON_CORTEX_A53, a_offset) { in TEST() argument
44654 TEST(GENERATE_F32_IGEMM_4X8__AARCH32_NEON_PRFM_CORTEX_A75, a_offset) { in TEST() argument
45153 TEST(GENERATE_F32_IGEMM_UPTO6X8__AARCH64_NEONFMA_PRFM_CORTEX_A75, a_offset) { in TEST() argument
45670 TEST(GENERATE_F32_IGEMM_1X8__AARCH64_NEONFMA_CORTEX_A75, a_offset) { in TEST() argument
46169 TEST(GENERATE_F32_IGEMM_1X8__AARCH64_NEONFMA_PRFM_CORTEX_A75, a_offset) { in TEST() argument
46668 TEST(GENERATE_F32_IGEMM_4X8__AARCH64_NEONFMA_PRFM_CORTEX_A75, a_offset) { in TEST() argument
47136 TEST(GENERATE_F32_IGEMM_6X8__AARCH64_NEONFMA_LD128, a_offset) { in TEST() argument