1799 void Riscv64Assembler::VLe8(VRegister vd, XRegister rs1, VM vm) {  in VLe8()  argument
1801   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLe8()
1802   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kUnitStride, vm);  in VLe8()
1806 void Riscv64Assembler::VLe16(VRegister vd, XRegister rs1, VM vm) {  in VLe16()  argument
1808   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLe16()
1809   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kUnitStride, vm);  in VLe16()
1813 void Riscv64Assembler::VLe32(VRegister vd, XRegister rs1, VM vm) {  in VLe32()  argument
1815   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLe32()
1816   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kUnitStride, vm);  in VLe32()
1820 void Riscv64Assembler::VLe64(VRegister vd, XRegister rs1, VM vm) {  in VLe64()  argument
1822   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLe64()
1823   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kUnitStride, vm);  in VLe64()
1827 void Riscv64Assembler::VSe8(VRegister vs3, XRegister rs1, VM vm) {  in VSe8()  argument
1829   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kUnitStride, vm);  in VSe8()
1833 void Riscv64Assembler::VSe16(VRegister vs3, XRegister rs1, VM vm) {  in VSe16()  argument
1835   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kUnitStride, vm);  in VSe16()
1839 void Riscv64Assembler::VSe32(VRegister vs3, XRegister rs1, VM vm) {  in VSe32()  argument
1841   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kUnitStride, vm);  in VSe32()
1845 void Riscv64Assembler::VSe64(VRegister vs3, XRegister rs1, VM vm) {  in VSe64()  argument
1847   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kUnitStride, vm);  in VSe64()
1853   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kUnitStride, VM::kUnmasked);  in VLm()
1859   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kUnitStride, VM::kUnmasked);  in VSm()
1865   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kUnitStride, VM::kUnmasked);  in VLe8ff()
1871   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kUnitStride, VM::kUnmasked);  in VLe16ff()
1877   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kUnitStride, VM::kUnmasked);  in VLe32ff()
1883   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kUnitStride, VM::kUnmasked);  in VLe64ff()
1887 void Riscv64Assembler::VLse8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLse8()  argument
1889   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLse8()
1890   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kStrided, vm);  in VLse8()
1894 void Riscv64Assembler::VLse16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLse16()  argument
1896   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLse16()
1897   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kStrided, vm);  in VLse16()
1901 void Riscv64Assembler::VLse32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLse32()  argument
1903   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLse32()
1904   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kStrided, vm);  in VLse32()
1908 void Riscv64Assembler::VLse64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLse64()  argument
1910   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLse64()
1911   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kStrided, vm);  in VLse64()
1915 void Riscv64Assembler::VSse8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSse8()  argument
1917   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kStrided, vm);  in VSse8()
1921 void Riscv64Assembler::VSse16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSse16()  argument
1923   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kStrided, vm);  in VSse16()
1927 void Riscv64Assembler::VSse32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSse32()  argument
1929   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kStrided, vm);  in VSse32()
1933 void Riscv64Assembler::VSse64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSse64()  argument
1935   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kStrided, vm);  in VSse64()
1939 void Riscv64Assembler::VLoxei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxei8()  argument
1941   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxei8()
1942   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxei8()
1946 void Riscv64Assembler::VLoxei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxei16()  argument
1948   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxei16()
1949   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxei16()
1953 void Riscv64Assembler::VLoxei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxei32()  argument
1955   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxei32()
1956   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxei32()
1960 void Riscv64Assembler::VLoxei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxei64()  argument
1962   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxei64()
1963   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxei64()
1967 void Riscv64Assembler::VLuxei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxei8()  argument
1969   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxei8()
1970   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxei8()
1974 void Riscv64Assembler::VLuxei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxei16()  argument
1976   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxei16()
1977   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxei16()
1981 void Riscv64Assembler::VLuxei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxei32()  argument
1983   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxei32()
1984   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxei32()
1988 void Riscv64Assembler::VLuxei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxei64()  argument
1990   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxei64()
1991   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxei64()
1995 void Riscv64Assembler::VSoxei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxei8()  argument
1997   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxei8()
2001 void Riscv64Assembler::VSoxei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxei16()  argument
2003   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxei16()
2007 void Riscv64Assembler::VSoxei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxei32()  argument
2009   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxei32()
2013 void Riscv64Assembler::VSoxei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxei64()  argument
2015   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxei64()
2019 void Riscv64Assembler::VSuxei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxei8()  argument
2021   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxei8()
2025 void Riscv64Assembler::VSuxei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxei16()  argument
2027   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxei16()
2031 void Riscv64Assembler::VSuxei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxei32()  argument
2033   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxei32()
2037 void Riscv64Assembler::VSuxei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxei64()  argument
2039   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxei64()
2043 void Riscv64Assembler::VLseg2e8(VRegister vd, XRegister rs1, VM vm) {  in VLseg2e8()  argument
2045   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg2e8()
2046   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg2e8()
2050 void Riscv64Assembler::VLseg2e16(VRegister vd, XRegister rs1, VM vm) {  in VLseg2e16()  argument
2052   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg2e16()
2053   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg2e16()
2057 void Riscv64Assembler::VLseg2e32(VRegister vd, XRegister rs1, VM vm) {  in VLseg2e32()  argument
2059   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg2e32()
2060   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg2e32()
2064 void Riscv64Assembler::VLseg2e64(VRegister vd, XRegister rs1, VM vm) {  in VLseg2e64()  argument
2066   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg2e64()
2067   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg2e64()
2071 void Riscv64Assembler::VLseg3e8(VRegister vd, XRegister rs1, VM vm) {  in VLseg3e8()  argument
2073   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg3e8()
2074   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg3e8()
2078 void Riscv64Assembler::VLseg3e16(VRegister vd, XRegister rs1, VM vm) {  in VLseg3e16()  argument
2080   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg3e16()
2081   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg3e16()
2085 void Riscv64Assembler::VLseg3e32(VRegister vd, XRegister rs1, VM vm) {  in VLseg3e32()  argument
2087   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg3e32()
2088   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg3e32()
2092 void Riscv64Assembler::VLseg3e64(VRegister vd, XRegister rs1, VM vm) {  in VLseg3e64()  argument
2094   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg3e64()
2095   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg3e64()
2099 void Riscv64Assembler::VLseg4e8(VRegister vd, XRegister rs1, VM vm) {  in VLseg4e8()  argument
2101   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg4e8()
2102   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg4e8()
2106 void Riscv64Assembler::VLseg4e16(VRegister vd, XRegister rs1, VM vm) {  in VLseg4e16()  argument
2108   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg4e16()
2109   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg4e16()
2113 void Riscv64Assembler::VLseg4e32(VRegister vd, XRegister rs1, VM vm) {  in VLseg4e32()  argument
2115   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg4e32()
2116   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg4e32()
2120 void Riscv64Assembler::VLseg4e64(VRegister vd, XRegister rs1, VM vm) {  in VLseg4e64()  argument
2122   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg4e64()
2123   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg4e64()
2127 void Riscv64Assembler::VLseg5e8(VRegister vd, XRegister rs1, VM vm) {  in VLseg5e8()  argument
2129   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg5e8()
2130   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg5e8()
2134 void Riscv64Assembler::VLseg5e16(VRegister vd, XRegister rs1, VM vm) {  in VLseg5e16()  argument
2136   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg5e16()
2137   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg5e16()
2141 void Riscv64Assembler::VLseg5e32(VRegister vd, XRegister rs1, VM vm) {  in VLseg5e32()  argument
2143   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg5e32()
2144   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg5e32()
2148 void Riscv64Assembler::VLseg5e64(VRegister vd, XRegister rs1, VM vm) {  in VLseg5e64()  argument
2150   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg5e64()
2151   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg5e64()
2155 void Riscv64Assembler::VLseg6e8(VRegister vd, XRegister rs1, VM vm) {  in VLseg6e8()  argument
2157   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg6e8()
2158   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg6e8()
2162 void Riscv64Assembler::VLseg6e16(VRegister vd, XRegister rs1, VM vm) {  in VLseg6e16()  argument
2164   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg6e16()
2165   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg6e16()
2169 void Riscv64Assembler::VLseg6e32(VRegister vd, XRegister rs1, VM vm) {  in VLseg6e32()  argument
2171   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg6e32()
2172   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg6e32()
2176 void Riscv64Assembler::VLseg6e64(VRegister vd, XRegister rs1, VM vm) {  in VLseg6e64()  argument
2178   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg6e64()
2179   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg6e64()
2183 void Riscv64Assembler::VLseg7e8(VRegister vd, XRegister rs1, VM vm) {  in VLseg7e8()  argument
2185   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg7e8()
2186   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg7e8()
2190 void Riscv64Assembler::VLseg7e16(VRegister vd, XRegister rs1, VM vm) {  in VLseg7e16()  argument
2192   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg7e16()
2193   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg7e16()
2197 void Riscv64Assembler::VLseg7e32(VRegister vd, XRegister rs1, VM vm) {  in VLseg7e32()  argument
2199   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg7e32()
2200   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg7e32()
2204 void Riscv64Assembler::VLseg7e64(VRegister vd, XRegister rs1, VM vm) {  in VLseg7e64()  argument
2206   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg7e64()
2207   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg7e64()
2211 void Riscv64Assembler::VLseg8e8(VRegister vd, XRegister rs1, VM vm) {  in VLseg8e8()  argument
2213   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg8e8()
2214   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg8e8()
2218 void Riscv64Assembler::VLseg8e16(VRegister vd, XRegister rs1, VM vm) {  in VLseg8e16()  argument
2220   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg8e16()
2221   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg8e16()
2225 void Riscv64Assembler::VLseg8e32(VRegister vd, XRegister rs1, VM vm) {  in VLseg8e32()  argument
2227   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg8e32()
2228   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg8e32()
2232 void Riscv64Assembler::VLseg8e64(VRegister vd, XRegister rs1, VM vm) {  in VLseg8e64()  argument
2234   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg8e64()
2235   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg8e64()
2239 void Riscv64Assembler::VSseg2e8(VRegister vs3, XRegister rs1, VM vm) {  in VSseg2e8()  argument
2241   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, vm);  in VSseg2e8()
2245 void Riscv64Assembler::VSseg2e16(VRegister vs3, XRegister rs1, VM vm) {  in VSseg2e16()  argument
2247   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, vm);  in VSseg2e16()
2251 void Riscv64Assembler::VSseg2e32(VRegister vs3, XRegister rs1, VM vm) {  in VSseg2e32()  argument
2253   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, vm);  in VSseg2e32()
2257 void Riscv64Assembler::VSseg2e64(VRegister vs3, XRegister rs1, VM vm) {  in VSseg2e64()  argument
2259   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, vm);  in VSseg2e64()
2263 void Riscv64Assembler::VSseg3e8(VRegister vs3, XRegister rs1, VM vm) {  in VSseg3e8()  argument
2265   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kUnitStride, vm);  in VSseg3e8()
2269 void Riscv64Assembler::VSseg3e16(VRegister vs3, XRegister rs1, VM vm) {  in VSseg3e16()  argument
2271   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kUnitStride, vm);  in VSseg3e16()
2275 void Riscv64Assembler::VSseg3e32(VRegister vs3, XRegister rs1, VM vm) {  in VSseg3e32()  argument
2277   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kUnitStride, vm);  in VSseg3e32()
2281 void Riscv64Assembler::VSseg3e64(VRegister vs3, XRegister rs1, VM vm) {  in VSseg3e64()  argument
2283   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kUnitStride, vm);  in VSseg3e64()
2287 void Riscv64Assembler::VSseg4e8(VRegister vs3, XRegister rs1, VM vm) {  in VSseg4e8()  argument
2289   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, vm);  in VSseg4e8()
2293 void Riscv64Assembler::VSseg4e16(VRegister vs3, XRegister rs1, VM vm) {  in VSseg4e16()  argument
2295   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, vm);  in VSseg4e16()
2299 void Riscv64Assembler::VSseg4e32(VRegister vs3, XRegister rs1, VM vm) {  in VSseg4e32()  argument
2301   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, vm);  in VSseg4e32()
2305 void Riscv64Assembler::VSseg4e64(VRegister vs3, XRegister rs1, VM vm) {  in VSseg4e64()  argument
2307   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, vm);  in VSseg4e64()
2311 void Riscv64Assembler::VSseg5e8(VRegister vs3, XRegister rs1, VM vm) {  in VSseg5e8()  argument
2313   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kUnitStride, vm);  in VSseg5e8()
2317 void Riscv64Assembler::VSseg5e16(VRegister vs3, XRegister rs1, VM vm) {  in VSseg5e16()  argument
2319   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kUnitStride, vm);  in VSseg5e16()
2323 void Riscv64Assembler::VSseg5e32(VRegister vs3, XRegister rs1, VM vm) {  in VSseg5e32()  argument
2325   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kUnitStride, vm);  in VSseg5e32()
2329 void Riscv64Assembler::VSseg5e64(VRegister vs3, XRegister rs1, VM vm) {  in VSseg5e64()  argument
2331   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kUnitStride, vm);  in VSseg5e64()
2335 void Riscv64Assembler::VSseg6e8(VRegister vs3, XRegister rs1, VM vm) {  in VSseg6e8()  argument
2337   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kUnitStride, vm);  in VSseg6e8()
2341 void Riscv64Assembler::VSseg6e16(VRegister vs3, XRegister rs1, VM vm) {  in VSseg6e16()  argument
2343   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kUnitStride, vm);  in VSseg6e16()
2347 void Riscv64Assembler::VSseg6e32(VRegister vs3, XRegister rs1, VM vm) {  in VSseg6e32()  argument
2349   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kUnitStride, vm);  in VSseg6e32()
2353 void Riscv64Assembler::VSseg6e64(VRegister vs3, XRegister rs1, VM vm) {  in VSseg6e64()  argument
2355   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kUnitStride, vm);  in VSseg6e64()
2359 void Riscv64Assembler::VSseg7e8(VRegister vs3, XRegister rs1, VM vm) {  in VSseg7e8()  argument
2361   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kUnitStride, vm);  in VSseg7e8()
2365 void Riscv64Assembler::VSseg7e16(VRegister vs3, XRegister rs1, VM vm) {  in VSseg7e16()  argument
2367   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kUnitStride, vm);  in VSseg7e16()
2371 void Riscv64Assembler::VSseg7e32(VRegister vs3, XRegister rs1, VM vm) {  in VSseg7e32()  argument
2373   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kUnitStride, vm);  in VSseg7e32()
2377 void Riscv64Assembler::VSseg7e64(VRegister vs3, XRegister rs1, VM vm) {  in VSseg7e64()  argument
2379   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kUnitStride, vm);  in VSseg7e64()
2383 void Riscv64Assembler::VSseg8e8(VRegister vs3, XRegister rs1, VM vm) {  in VSseg8e8()  argument
2385   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, vm);  in VSseg8e8()
2389 void Riscv64Assembler::VSseg8e16(VRegister vs3, XRegister rs1, VM vm) {  in VSseg8e16()  argument
2391   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, vm);  in VSseg8e16()
2395 void Riscv64Assembler::VSseg8e32(VRegister vs3, XRegister rs1, VM vm) {  in VSseg8e32()  argument
2397   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, vm);  in VSseg8e32()
2401 void Riscv64Assembler::VSseg8e64(VRegister vs3, XRegister rs1, VM vm) {  in VSseg8e64()  argument
2403   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, vm);  in VSseg8e64()
2407 void Riscv64Assembler::VLseg2e8ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg2e8ff()  argument
2409   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg2e8ff()
2410   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg2e8ff()
2414 void Riscv64Assembler::VLseg2e16ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg2e16ff()  argument
2416   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg2e16ff()
2417   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg2e16ff()
2421 void Riscv64Assembler::VLseg2e32ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg2e32ff()  argument
2423   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg2e32ff()
2424   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg2e32ff()
2428 void Riscv64Assembler::VLseg2e64ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg2e64ff()  argument
2430   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg2e64ff()
2431   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg2e64ff()
2435 void Riscv64Assembler::VLseg3e8ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg3e8ff()  argument
2437   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg3e8ff()
2438   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg3e8ff()
2442 void Riscv64Assembler::VLseg3e16ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg3e16ff()  argument
2444   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg3e16ff()
2445   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg3e16ff()
2449 void Riscv64Assembler::VLseg3e32ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg3e32ff()  argument
2451   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg3e32ff()
2452   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg3e32ff()
2456 void Riscv64Assembler::VLseg3e64ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg3e64ff()  argument
2458   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg3e64ff()
2459   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg3e64ff()
2463 void Riscv64Assembler::VLseg4e8ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg4e8ff()  argument
2465   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg4e8ff()
2466   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg4e8ff()
2470 void Riscv64Assembler::VLseg4e16ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg4e16ff()  argument
2472   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg4e16ff()
2473   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg4e16ff()
2477 void Riscv64Assembler::VLseg4e32ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg4e32ff()  argument
2479   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg4e32ff()
2480   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg4e32ff()
2484 void Riscv64Assembler::VLseg4e64ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg4e64ff()  argument
2486   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg4e64ff()
2487   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg4e64ff()
2491 void Riscv64Assembler::VLseg5e8ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg5e8ff()  argument
2493   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg5e8ff()
2494   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg5e8ff()
2498 void Riscv64Assembler::VLseg5e16ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg5e16ff()  argument
2500   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg5e16ff()
2501   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg5e16ff()
2505 void Riscv64Assembler::VLseg5e32ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg5e32ff()  argument
2507   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg5e32ff()
2508   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg5e32ff()
2512 void Riscv64Assembler::VLseg5e64ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg5e64ff()  argument
2514   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg5e64ff()
2515   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg5e64ff()
2519 void Riscv64Assembler::VLseg6e8ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg6e8ff()  argument
2521   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg6e8ff()
2522   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg6e8ff()
2526 void Riscv64Assembler::VLseg6e16ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg6e16ff()  argument
2528   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg6e16ff()
2529   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg6e16ff()
2533 void Riscv64Assembler::VLseg6e32ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg6e32ff()  argument
2535   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg6e32ff()
2536   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg6e32ff()
2540 void Riscv64Assembler::VLseg6e64ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg6e64ff()  argument
2542   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg6e64ff()
2543   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg6e64ff()
2547 void Riscv64Assembler::VLseg7e8ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg7e8ff()  argument
2549   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg7e8ff()
2550   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg7e8ff()
2554 void Riscv64Assembler::VLseg7e16ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg7e16ff()  argument
2556   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg7e16ff()
2557   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg7e16ff()
2561 void Riscv64Assembler::VLseg7e32ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg7e32ff()  argument
2563   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg7e32ff()
2564   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg7e32ff()
2568 void Riscv64Assembler::VLseg7e64ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg7e64ff()  argument
2570   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg7e64ff()
2571   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg7e64ff()
2575 void Riscv64Assembler::VLseg8e8ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg8e8ff()  argument
2577   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg8e8ff()
2578   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg8e8ff()
2582 void Riscv64Assembler::VLseg8e16ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg8e16ff()  argument
2584   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg8e16ff()
2585   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg8e16ff()
2589 void Riscv64Assembler::VLseg8e32ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg8e32ff()  argument
2591   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg8e32ff()
2592   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg8e32ff()
2596 void Riscv64Assembler::VLseg8e64ff(VRegister vd, XRegister rs1, VM vm) {  in VLseg8e64ff()  argument
2598   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLseg8e64ff()
2599   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, vm);  in VLseg8e64ff()
2603 void Riscv64Assembler::VLsseg2e8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg2e8()  argument
2605   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLsseg2e8()
2606   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kStrided, vm);  in VLsseg2e8()
2610 void Riscv64Assembler::VLsseg2e16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg2e16()  argument
2612   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLsseg2e16()
2613   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kStrided, vm);  in VLsseg2e16()
2617 void Riscv64Assembler::VLsseg2e32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg2e32()  argument
2619   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLsseg2e32()
2620   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kStrided, vm);  in VLsseg2e32()
2624 void Riscv64Assembler::VLsseg2e64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg2e64()  argument
2626   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLsseg2e64()
2627   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kStrided, vm);  in VLsseg2e64()
2631 void Riscv64Assembler::VLsseg3e8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg3e8()  argument
2633   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLsseg3e8()
2634   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kStrided, vm);  in VLsseg3e8()
2638 void Riscv64Assembler::VLsseg3e16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg3e16()  argument
2640   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLsseg3e16()
2641   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kStrided, vm);  in VLsseg3e16()
2645 void Riscv64Assembler::VLsseg3e32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg3e32()  argument
2647   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLsseg3e32()
2648   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kStrided, vm);  in VLsseg3e32()
2652 void Riscv64Assembler::VLsseg3e64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg3e64()  argument
2654   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLsseg3e64()
2655   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kStrided, vm);  in VLsseg3e64()
2659 void Riscv64Assembler::VLsseg4e8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg4e8()  argument
2661   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLsseg4e8()
2662   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kStrided, vm);  in VLsseg4e8()
2666 void Riscv64Assembler::VLsseg4e16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg4e16()  argument
2668   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLsseg4e16()
2669   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kStrided, vm);  in VLsseg4e16()
2673 void Riscv64Assembler::VLsseg4e32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg4e32()  argument
2675   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLsseg4e32()
2676   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kStrided, vm);  in VLsseg4e32()
2680 void Riscv64Assembler::VLsseg4e64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg4e64()  argument
2682   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLsseg4e64()
2683   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kStrided, vm);  in VLsseg4e64()
2687 void Riscv64Assembler::VLsseg5e8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg5e8()  argument
2689   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLsseg5e8()
2690   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kStrided, vm);  in VLsseg5e8()
2694 void Riscv64Assembler::VLsseg5e16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg5e16()  argument
2696   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLsseg5e16()
2697   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kStrided, vm);  in VLsseg5e16()
2701 void Riscv64Assembler::VLsseg5e32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg5e32()  argument
2703   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLsseg5e32()
2704   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kStrided, vm);  in VLsseg5e32()
2708 void Riscv64Assembler::VLsseg5e64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg5e64()  argument
2710   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLsseg5e64()
2711   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kStrided, vm);  in VLsseg5e64()
2715 void Riscv64Assembler::VLsseg6e8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg6e8()  argument
2717   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLsseg6e8()
2718   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kStrided, vm);  in VLsseg6e8()
2722 void Riscv64Assembler::VLsseg6e16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg6e16()  argument
2724   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLsseg6e16()
2725   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kStrided, vm);  in VLsseg6e16()
2729 void Riscv64Assembler::VLsseg6e32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg6e32()  argument
2731   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLsseg6e32()
2732   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kStrided, vm);  in VLsseg6e32()
2736 void Riscv64Assembler::VLsseg6e64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg6e64()  argument
2738   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLsseg6e64()
2739   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kStrided, vm);  in VLsseg6e64()
2743 void Riscv64Assembler::VLsseg7e8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg7e8()  argument
2745   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLsseg7e8()
2746   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kStrided, vm);  in VLsseg7e8()
2750 void Riscv64Assembler::VLsseg7e16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg7e16()  argument
2752   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLsseg7e16()
2753   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kStrided, vm);  in VLsseg7e16()
2757 void Riscv64Assembler::VLsseg7e32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg7e32()  argument
2759   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLsseg7e32()
2760   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kStrided, vm);  in VLsseg7e32()
2764 void Riscv64Assembler::VLsseg7e64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg7e64()  argument
2766   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLsseg7e64()
2767   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kStrided, vm);  in VLsseg7e64()
2771 void Riscv64Assembler::VLsseg8e8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg8e8()  argument
2773   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLsseg8e8()
2774   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kStrided, vm);  in VLsseg8e8()
2778 void Riscv64Assembler::VLsseg8e16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg8e16()  argument
2780   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLsseg8e16()
2781   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kStrided, vm);  in VLsseg8e16()
2785 void Riscv64Assembler::VLsseg8e32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg8e32()  argument
2787   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLsseg8e32()
2788   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kStrided, vm);  in VLsseg8e32()
2792 void Riscv64Assembler::VLsseg8e64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) {  in VLsseg8e64()  argument
2794   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLsseg8e64()
2795   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kStrided, vm);  in VLsseg8e64()
2799 void Riscv64Assembler::VSsseg2e8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg2e8()  argument
2801   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kStrided, vm);  in VSsseg2e8()
2805 void Riscv64Assembler::VSsseg2e16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg2e16()  argument
2807   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kStrided, vm);  in VSsseg2e16()
2811 void Riscv64Assembler::VSsseg2e32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg2e32()  argument
2813   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kStrided, vm);  in VSsseg2e32()
2817 void Riscv64Assembler::VSsseg2e64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg2e64()  argument
2819   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kStrided, vm);  in VSsseg2e64()
2823 void Riscv64Assembler::VSsseg3e8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg3e8()  argument
2825   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kStrided, vm);  in VSsseg3e8()
2829 void Riscv64Assembler::VSsseg3e16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg3e16()  argument
2831   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kStrided, vm);  in VSsseg3e16()
2835 void Riscv64Assembler::VSsseg3e32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg3e32()  argument
2837   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kStrided, vm);  in VSsseg3e32()
2841 void Riscv64Assembler::VSsseg3e64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg3e64()  argument
2843   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kStrided, vm);  in VSsseg3e64()
2847 void Riscv64Assembler::VSsseg4e8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg4e8()  argument
2849   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kStrided, vm);  in VSsseg4e8()
2853 void Riscv64Assembler::VSsseg4e16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg4e16()  argument
2855   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kStrided, vm);  in VSsseg4e16()
2859 void Riscv64Assembler::VSsseg4e32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg4e32()  argument
2861   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kStrided, vm);  in VSsseg4e32()
2865 void Riscv64Assembler::VSsseg4e64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg4e64()  argument
2867   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kStrided, vm);  in VSsseg4e64()
2871 void Riscv64Assembler::VSsseg5e8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg5e8()  argument
2873   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kStrided, vm);  in VSsseg5e8()
2877 void Riscv64Assembler::VSsseg5e16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg5e16()  argument
2879   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kStrided, vm);  in VSsseg5e16()
2883 void Riscv64Assembler::VSsseg5e32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg5e32()  argument
2885   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kStrided, vm);  in VSsseg5e32()
2889 void Riscv64Assembler::VSsseg5e64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg5e64()  argument
2891   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kStrided, vm);  in VSsseg5e64()
2895 void Riscv64Assembler::VSsseg6e8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg6e8()  argument
2897   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kStrided, vm);  in VSsseg6e8()
2901 void Riscv64Assembler::VSsseg6e16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg6e16()  argument
2903   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kStrided, vm);  in VSsseg6e16()
2907 void Riscv64Assembler::VSsseg6e32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg6e32()  argument
2909   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kStrided, vm);  in VSsseg6e32()
2913 void Riscv64Assembler::VSsseg6e64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg6e64()  argument
2915   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kStrided, vm);  in VSsseg6e64()
2919 void Riscv64Assembler::VSsseg7e8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg7e8()  argument
2921   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kStrided, vm);  in VSsseg7e8()
2925 void Riscv64Assembler::VSsseg7e16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg7e16()  argument
2927   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kStrided, vm);  in VSsseg7e16()
2931 void Riscv64Assembler::VSsseg7e32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg7e32()  argument
2933   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kStrided, vm);  in VSsseg7e32()
2937 void Riscv64Assembler::VSsseg7e64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg7e64()  argument
2939   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kStrided, vm);  in VSsseg7e64()
2943 void Riscv64Assembler::VSsseg8e8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg8e8()  argument
2945   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kStrided, vm);  in VSsseg8e8()
2949 void Riscv64Assembler::VSsseg8e16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg8e16()  argument
2951   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kStrided, vm);  in VSsseg8e16()
2955 void Riscv64Assembler::VSsseg8e32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg8e32()  argument
2957   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kStrided, vm);  in VSsseg8e32()
2961 void Riscv64Assembler::VSsseg8e64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) {  in VSsseg8e64()  argument
2963   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kStrided, vm);  in VSsseg8e64()
2967 void Riscv64Assembler::VLuxseg2ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg2ei8()  argument
2969   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxseg2ei8()
2970   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxseg2ei8()
2974 void Riscv64Assembler::VLuxseg2ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg2ei16()  argument
2976   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxseg2ei16()
2977   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxseg2ei16()
2981 void Riscv64Assembler::VLuxseg2ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg2ei32()  argument
2983   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxseg2ei32()
2984   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxseg2ei32()
2988 void Riscv64Assembler::VLuxseg2ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg2ei64()  argument
2990   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxseg2ei64()
2991   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxseg2ei64()
2995 void Riscv64Assembler::VLuxseg3ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg3ei8()  argument
2997   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxseg3ei8()
2998   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxseg3ei8()
3002 void Riscv64Assembler::VLuxseg3ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg3ei16()  argument
3004   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxseg3ei16()
3005   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxseg3ei16()
3009 void Riscv64Assembler::VLuxseg3ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg3ei32()  argument
3011   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxseg3ei32()
3012   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxseg3ei32()
3016 void Riscv64Assembler::VLuxseg3ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg3ei64()  argument
3018   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxseg3ei64()
3019   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxseg3ei64()
3023 void Riscv64Assembler::VLuxseg4ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg4ei8()  argument
3025   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxseg4ei8()
3026   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxseg4ei8()
3030 void Riscv64Assembler::VLuxseg4ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg4ei16()  argument
3032   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxseg4ei16()
3033   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxseg4ei16()
3037 void Riscv64Assembler::VLuxseg4ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg4ei32()  argument
3039   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxseg4ei32()
3040   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxseg4ei32()
3044 void Riscv64Assembler::VLuxseg4ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg4ei64()  argument
3046   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxseg4ei64()
3047   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxseg4ei64()
3051 void Riscv64Assembler::VLuxseg5ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg5ei8()  argument
3053   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxseg5ei8()
3054   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxseg5ei8()
3058 void Riscv64Assembler::VLuxseg5ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg5ei16()  argument
3060   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxseg5ei16()
3061   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxseg5ei16()
3065 void Riscv64Assembler::VLuxseg5ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg5ei32()  argument
3067   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxseg5ei32()
3068   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxseg5ei32()
3072 void Riscv64Assembler::VLuxseg5ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg5ei64()  argument
3074   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxseg5ei64()
3075   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxseg5ei64()
3079 void Riscv64Assembler::VLuxseg6ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg6ei8()  argument
3081   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxseg6ei8()
3082   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxseg6ei8()
3086 void Riscv64Assembler::VLuxseg6ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg6ei16()  argument
3088   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxseg6ei16()
3089   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxseg6ei16()
3093 void Riscv64Assembler::VLuxseg6ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg6ei32()  argument
3095   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxseg6ei32()
3096   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxseg6ei32()
3100 void Riscv64Assembler::VLuxseg6ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg6ei64()  argument
3102   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxseg6ei64()
3103   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxseg6ei64()
3107 void Riscv64Assembler::VLuxseg7ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg7ei8()  argument
3109   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxseg7ei8()
3110   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxseg7ei8()
3114 void Riscv64Assembler::VLuxseg7ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg7ei16()  argument
3116   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxseg7ei16()
3117   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxseg7ei16()
3121 void Riscv64Assembler::VLuxseg7ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg7ei32()  argument
3123   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxseg7ei32()
3124   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxseg7ei32()
3128 void Riscv64Assembler::VLuxseg7ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg7ei64()  argument
3130   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxseg7ei64()
3131   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxseg7ei64()
3135 void Riscv64Assembler::VLuxseg8ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg8ei8()  argument
3137   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxseg8ei8()
3138   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxseg8ei8()
3142 void Riscv64Assembler::VLuxseg8ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg8ei16()  argument
3144   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxseg8ei16()
3145   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxseg8ei16()
3149 void Riscv64Assembler::VLuxseg8ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg8ei32()  argument
3151   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxseg8ei32()
3152   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxseg8ei32()
3156 void Riscv64Assembler::VLuxseg8ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLuxseg8ei64()  argument
3158   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLuxseg8ei64()
3159   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VLuxseg8ei64()
3163 void Riscv64Assembler::VSuxseg2ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg2ei8()  argument
3165   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxseg2ei8()
3169 void Riscv64Assembler::VSuxseg2ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg2ei16()  argument
3171   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxseg2ei16()
3175 void Riscv64Assembler::VSuxseg2ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg2ei32()  argument
3177   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxseg2ei32()
3181 void Riscv64Assembler::VSuxseg2ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg2ei64()  argument
3183   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxseg2ei64()
3187 void Riscv64Assembler::VSuxseg3ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg3ei8()  argument
3189   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxseg3ei8()
3193 void Riscv64Assembler::VSuxseg3ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg3ei16()  argument
3195   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxseg3ei16()
3199 void Riscv64Assembler::VSuxseg3ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg3ei32()  argument
3201   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxseg3ei32()
3205 void Riscv64Assembler::VSuxseg3ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg3ei64()  argument
3207   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxseg3ei64()
3211 void Riscv64Assembler::VSuxseg4ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg4ei8()  argument
3213   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxseg4ei8()
3217 void Riscv64Assembler::VSuxseg4ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg4ei16()  argument
3219   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxseg4ei16()
3223 void Riscv64Assembler::VSuxseg4ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg4ei32()  argument
3225   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxseg4ei32()
3229 void Riscv64Assembler::VSuxseg4ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg4ei64()  argument
3231   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxseg4ei64()
3235 void Riscv64Assembler::VSuxseg5ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg5ei8()  argument
3237   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxseg5ei8()
3241 void Riscv64Assembler::VSuxseg5ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg5ei16()  argument
3243   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxseg5ei16()
3247 void Riscv64Assembler::VSuxseg5ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg5ei32()  argument
3249   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxseg5ei32()
3253 void Riscv64Assembler::VSuxseg5ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg5ei64()  argument
3255   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxseg5ei64()
3259 void Riscv64Assembler::VSuxseg6ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg6ei8()  argument
3261   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxseg6ei8()
3265 void Riscv64Assembler::VSuxseg6ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg6ei16()  argument
3267   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxseg6ei16()
3271 void Riscv64Assembler::VSuxseg6ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg6ei32()  argument
3273   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxseg6ei32()
3277 void Riscv64Assembler::VSuxseg6ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg6ei64()  argument
3279   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxseg6ei64()
3283 void Riscv64Assembler::VSuxseg7ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg7ei8()  argument
3285   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxseg7ei8()
3289 void Riscv64Assembler::VSuxseg7ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg7ei16()  argument
3291   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxseg7ei16()
3295 void Riscv64Assembler::VSuxseg7ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg7ei32()  argument
3297   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxseg7ei32()
3301 void Riscv64Assembler::VSuxseg7ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg7ei64()  argument
3303   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxseg7ei64()
3307 void Riscv64Assembler::VSuxseg8ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg8ei8()  argument
3309   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxseg8ei8()
3313 void Riscv64Assembler::VSuxseg8ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg8ei16()  argument
3315   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxseg8ei16()
3319 void Riscv64Assembler::VSuxseg8ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg8ei32()  argument
3321   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxseg8ei32()
3325 void Riscv64Assembler::VSuxseg8ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSuxseg8ei64()  argument
3327   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedUnordered, vm);  in VSuxseg8ei64()
3331 void Riscv64Assembler::VLoxseg2ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg2ei8()  argument
3333   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxseg2ei8()
3334   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxseg2ei8()
3338 void Riscv64Assembler::VLoxseg2ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg2ei16()  argument
3340   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxseg2ei16()
3341   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxseg2ei16()
3345 void Riscv64Assembler::VLoxseg2ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg2ei32()  argument
3347   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxseg2ei32()
3348   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxseg2ei32()
3352 void Riscv64Assembler::VLoxseg2ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg2ei64()  argument
3354   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxseg2ei64()
3355   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxseg2ei64()
3359 void Riscv64Assembler::VLoxseg3ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg3ei8()  argument
3361   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxseg3ei8()
3362   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxseg3ei8()
3366 void Riscv64Assembler::VLoxseg3ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg3ei16()  argument
3368   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxseg3ei16()
3369   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxseg3ei16()
3373 void Riscv64Assembler::VLoxseg3ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg3ei32()  argument
3375   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxseg3ei32()
3376   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxseg3ei32()
3380 void Riscv64Assembler::VLoxseg3ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg3ei64()  argument
3382   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxseg3ei64()
3383   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxseg3ei64()
3387 void Riscv64Assembler::VLoxseg4ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg4ei8()  argument
3389   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxseg4ei8()
3390   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxseg4ei8()
3394 void Riscv64Assembler::VLoxseg4ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg4ei16()  argument
3396   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxseg4ei16()
3397   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxseg4ei16()
3401 void Riscv64Assembler::VLoxseg4ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg4ei32()  argument
3403   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxseg4ei32()
3404   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxseg4ei32()
3408 void Riscv64Assembler::VLoxseg4ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg4ei64()  argument
3410   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxseg4ei64()
3411   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxseg4ei64()
3415 void Riscv64Assembler::VLoxseg5ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg5ei8()  argument
3417   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxseg5ei8()
3418   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxseg5ei8()
3422 void Riscv64Assembler::VLoxseg5ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg5ei16()  argument
3424   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxseg5ei16()
3425   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxseg5ei16()
3429 void Riscv64Assembler::VLoxseg5ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg5ei32()  argument
3431   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxseg5ei32()
3432   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxseg5ei32()
3436 void Riscv64Assembler::VLoxseg5ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg5ei64()  argument
3438   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxseg5ei64()
3439   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxseg5ei64()
3443 void Riscv64Assembler::VLoxseg6ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg6ei8()  argument
3445   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxseg6ei8()
3446   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxseg6ei8()
3450 void Riscv64Assembler::VLoxseg6ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg6ei16()  argument
3452   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxseg6ei16()
3453   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxseg6ei16()
3457 void Riscv64Assembler::VLoxseg6ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg6ei32()  argument
3459   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxseg6ei32()
3460   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxseg6ei32()
3464 void Riscv64Assembler::VLoxseg6ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg6ei64()  argument
3466   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxseg6ei64()
3467   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxseg6ei64()
3471 void Riscv64Assembler::VLoxseg7ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg7ei8()  argument
3473   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxseg7ei8()
3474   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxseg7ei8()
3478 void Riscv64Assembler::VLoxseg7ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg7ei16()  argument
3480   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxseg7ei16()
3481   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxseg7ei16()
3485 void Riscv64Assembler::VLoxseg7ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg7ei32()  argument
3487   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxseg7ei32()
3488   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxseg7ei32()
3492 void Riscv64Assembler::VLoxseg7ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg7ei64()  argument
3494   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxseg7ei64()
3495   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxseg7ei64()
3499 void Riscv64Assembler::VLoxseg8ei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg8ei8()  argument
3501   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxseg8ei8()
3502   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxseg8ei8()
3506 void Riscv64Assembler::VLoxseg8ei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg8ei16()  argument
3508   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxseg8ei16()
3509   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxseg8ei16()
3513 void Riscv64Assembler::VLoxseg8ei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg8ei32()  argument
3515   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxseg8ei32()
3516   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxseg8ei32()
3520 void Riscv64Assembler::VLoxseg8ei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VLoxseg8ei64()  argument
3522   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VLoxseg8ei64()
3523   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VLoxseg8ei64()
3527 void Riscv64Assembler::VSoxseg2ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg2ei8()  argument
3529   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxseg2ei8()
3533 void Riscv64Assembler::VSoxseg2ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg2ei16()  argument
3535   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxseg2ei16()
3539 void Riscv64Assembler::VSoxseg2ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg2ei32()  argument
3541   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxseg2ei32()
3545 void Riscv64Assembler::VSoxseg2ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg2ei64()  argument
3547   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxseg2ei64()
3551 void Riscv64Assembler::VSoxseg3ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg3ei8()  argument
3553   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxseg3ei8()
3557 void Riscv64Assembler::VSoxseg3ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg3ei16()  argument
3559   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxseg3ei16()
3563 void Riscv64Assembler::VSoxseg3ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg3ei32()  argument
3565   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxseg3ei32()
3569 void Riscv64Assembler::VSoxseg3ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg3ei64()  argument
3571   const uint32_t funct7 = EncodeRVVMemF7(Nf::k3, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxseg3ei64()
3575 void Riscv64Assembler::VSoxseg4ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg4ei8()  argument
3577   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxseg4ei8()
3581 void Riscv64Assembler::VSoxseg4ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg4ei16()  argument
3583   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxseg4ei16()
3587 void Riscv64Assembler::VSoxseg4ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg4ei32()  argument
3589   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxseg4ei32()
3593 void Riscv64Assembler::VSoxseg4ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg4ei64()  argument
3595   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxseg4ei64()
3599 void Riscv64Assembler::VSoxseg5ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg5ei8()  argument
3601   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxseg5ei8()
3605 void Riscv64Assembler::VSoxseg5ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg5ei16()  argument
3607   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxseg5ei16()
3611 void Riscv64Assembler::VSoxseg5ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg5ei32()  argument
3613   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxseg5ei32()
3617 void Riscv64Assembler::VSoxseg5ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg5ei64()  argument
3619   const uint32_t funct7 = EncodeRVVMemF7(Nf::k5, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxseg5ei64()
3623 void Riscv64Assembler::VSoxseg6ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg6ei8()  argument
3625   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxseg6ei8()
3629 void Riscv64Assembler::VSoxseg6ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg6ei16()  argument
3631   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxseg6ei16()
3635 void Riscv64Assembler::VSoxseg6ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg6ei32()  argument
3637   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxseg6ei32()
3641 void Riscv64Assembler::VSoxseg6ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg6ei64()  argument
3643   const uint32_t funct7 = EncodeRVVMemF7(Nf::k6, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxseg6ei64()
3647 void Riscv64Assembler::VSoxseg7ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg7ei8()  argument
3649   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxseg7ei8()
3653 void Riscv64Assembler::VSoxseg7ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg7ei16()  argument
3655   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxseg7ei16()
3659 void Riscv64Assembler::VSoxseg7ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg7ei32()  argument
3661   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxseg7ei32()
3665 void Riscv64Assembler::VSoxseg7ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg7ei64()  argument
3667   const uint32_t funct7 = EncodeRVVMemF7(Nf::k7, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxseg7ei64()
3671 void Riscv64Assembler::VSoxseg8ei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg8ei8()  argument
3673   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxseg8ei8()
3677 void Riscv64Assembler::VSoxseg8ei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg8ei16()  argument
3679   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxseg8ei16()
3683 void Riscv64Assembler::VSoxseg8ei32(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg8ei32()  argument
3685   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxseg8ei32()
3689 void Riscv64Assembler::VSoxseg8ei64(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) {  in VSoxseg8ei64()  argument
3691   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kIndexedOrdered, vm);  in VSoxseg8ei64()
3697   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kUnitStride, VM::kUnmasked);  in VL1re8()
3703   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kUnitStride, VM::kUnmasked);  in VL1re16()
3709   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kUnitStride, VM::kUnmasked);  in VL1re32()
3715   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kUnitStride, VM::kUnmasked);  in VL1re64()
3722   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, VM::kUnmasked);  in VL2re8()
3729   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, VM::kUnmasked);  in VL2re16()
3736   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, VM::kUnmasked);  in VL2re32()
3743   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, VM::kUnmasked);  in VL2re64()
3750   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, VM::kUnmasked);  in VL4re8()
3757   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, VM::kUnmasked);  in VL4re16()
3764   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, VM::kUnmasked);  in VL4re32()
3771   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, VM::kUnmasked);  in VL4re64()
3778   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, VM::kUnmasked);  in VL8re8()
3785   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, VM::kUnmasked);  in VL8re16()
3792   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, VM::kUnmasked);  in VL8re32()
3799   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, VM::kUnmasked);  in VL8re64()
3813   const uint32_t funct7 = EncodeRVVMemF7(Nf::k1, 0x0, MemAddressMode::kUnitStride, VM::kUnmasked);  in VS1r()
3819   const uint32_t funct7 = EncodeRVVMemF7(Nf::k2, 0x0, MemAddressMode::kUnitStride, VM::kUnmasked);  in VS2r()
3825   const uint32_t funct7 = EncodeRVVMemF7(Nf::k4, 0x0, MemAddressMode::kUnitStride, VM::kUnmasked);  in VS4r()
3831   const uint32_t funct7 = EncodeRVVMemF7(Nf::k8, 0x0, MemAddressMode::kUnitStride, VM::kUnmasked);  in VS8r()
3839 void Riscv64Assembler::VAdd_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VAdd_vv()  argument
3841   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VAdd_vv()
3842   const uint32_t funct7 = EncodeRVVF7(0b000000, vm);  in VAdd_vv()
3846 void Riscv64Assembler::VAdd_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VAdd_vx()  argument
3848   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VAdd_vx()
3849   const uint32_t funct7 = EncodeRVVF7(0b000000, vm);  in VAdd_vx()
3853 void Riscv64Assembler::VAdd_vi(VRegister vd, VRegister vs2, int32_t imm5, VM vm) {  in VAdd_vi()  argument
3855   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VAdd_vi()
3856   const uint32_t funct7 = EncodeRVVF7(0b000000, vm);  in VAdd_vi()
3860 void Riscv64Assembler::VSub_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VSub_vv()  argument
3862   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSub_vv()
3863   const uint32_t funct7 = EncodeRVVF7(0b000010, vm);  in VSub_vv()
3867 void Riscv64Assembler::VSub_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSub_vx()  argument
3869   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSub_vx()
3870   const uint32_t funct7 = EncodeRVVF7(0b000010, vm);  in VSub_vx()
3874 void Riscv64Assembler::VRsub_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VRsub_vx()  argument
3876   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VRsub_vx()
3877   const uint32_t funct7 = EncodeRVVF7(0b000011, vm);  in VRsub_vx()
3881 void Riscv64Assembler::VRsub_vi(VRegister vd, VRegister vs2, int32_t imm5, VM vm) {  in VRsub_vi()  argument
3883   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VRsub_vi()
3884   const uint32_t funct7 = EncodeRVVF7(0b000011, vm);  in VRsub_vi()
3890 void Riscv64Assembler::VMinu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VMinu_vv()  argument
3892   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMinu_vv()
3893   const uint32_t funct7 = EncodeRVVF7(0b000100, vm);  in VMinu_vv()
3897 void Riscv64Assembler::VMinu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMinu_vx()  argument
3899   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMinu_vx()
3900   const uint32_t funct7 = EncodeRVVF7(0b000100, vm);  in VMinu_vx()
3904 void Riscv64Assembler::VMin_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VMin_vv()  argument
3906   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMin_vv()
3907   const uint32_t funct7 = EncodeRVVF7(0b000101, vm);  in VMin_vv()
3911 void Riscv64Assembler::VMin_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMin_vx()  argument
3913   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMin_vx()
3914   const uint32_t funct7 = EncodeRVVF7(0b000101, vm);  in VMin_vx()
3918 void Riscv64Assembler::VMaxu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VMaxu_vv()  argument
3920   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMaxu_vv()
3921   const uint32_t funct7 = EncodeRVVF7(0b000110, vm);  in VMaxu_vv()
3925 void Riscv64Assembler::VMaxu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMaxu_vx()  argument
3927   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMaxu_vx()
3928   const uint32_t funct7 = EncodeRVVF7(0b000110, vm);  in VMaxu_vx()
3932 void Riscv64Assembler::VMax_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VMax_vv()  argument
3934   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMax_vv()
3935   const uint32_t funct7 = EncodeRVVF7(0b000111, vm);  in VMax_vv()
3939 void Riscv64Assembler::VMax_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMax_vx()  argument
3941   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMax_vx()
3942   const uint32_t funct7 = EncodeRVVF7(0b000111, vm);  in VMax_vx()
3946 void Riscv64Assembler::VAnd_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VAnd_vv()  argument
3948   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VAnd_vv()
3949   const uint32_t funct7 = EncodeRVVF7(0b001001, vm);  in VAnd_vv()
3953 void Riscv64Assembler::VAnd_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VAnd_vx()  argument
3955   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VAnd_vx()
3956   const uint32_t funct7 = EncodeRVVF7(0b001001, vm);  in VAnd_vx()
3960 void Riscv64Assembler::VAnd_vi(VRegister vd, VRegister vs2, int32_t imm5, VM vm) {  in VAnd_vi()  argument
3962   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VAnd_vi()
3963   const uint32_t funct7 = EncodeRVVF7(0b001001, vm);  in VAnd_vi()
3967 void Riscv64Assembler::VOr_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VOr_vv()  argument
3969   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VOr_vv()
3970   const uint32_t funct7 = EncodeRVVF7(0b001010, vm);  in VOr_vv()
3974 void Riscv64Assembler::VOr_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VOr_vx()  argument
3976   const uint32_t funct7 = EncodeRVVF7(0b001010, vm);  in VOr_vx()
3980 void Riscv64Assembler::VOr_vi(VRegister vd, VRegister vs2, int32_t imm5, VM vm) {  in VOr_vi()  argument
3982   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VOr_vi()
3983   const uint32_t funct7 = EncodeRVVF7(0b001010, vm);  in VOr_vi()
3987 void Riscv64Assembler::VXor_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VXor_vv()  argument
3989   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VXor_vv()
3990   const uint32_t funct7 = EncodeRVVF7(0b001011, vm);  in VXor_vv()
3994 void Riscv64Assembler::VXor_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VXor_vx()  argument
3996   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VXor_vx()
3997   const uint32_t funct7 = EncodeRVVF7(0b001011, vm);  in VXor_vx()
4001 void Riscv64Assembler::VXor_vi(VRegister vd, VRegister vs2, int32_t imm5, VM vm) {  in VXor_vi()  argument
4003   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VXor_vi()
4004   const uint32_t funct7 = EncodeRVVF7(0b001011, vm);  in VXor_vi()
4008 void Riscv64Assembler::VNot_v(VRegister vd, VRegister vs2, VM vm) { VXor_vi(vd, vs2, -1, vm); }  in VNot_v()  argument
4010 void Riscv64Assembler::VRgather_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VRgather_vv()  argument
4012   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VRgather_vv()
4015   const uint32_t funct7 = EncodeRVVF7(0b001100, vm);  in VRgather_vv()
4019 void Riscv64Assembler::VRgather_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VRgather_vx()  argument
4021   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VRgather_vx()
4023   const uint32_t funct7 = EncodeRVVF7(0b001100, vm);  in VRgather_vx()
4027 void Riscv64Assembler::VRgather_vi(VRegister vd, VRegister vs2, uint32_t uimm5, VM vm) {  in VRgather_vi()  argument
4029   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VRgather_vi()
4031   const uint32_t funct7 = EncodeRVVF7(0b001100, vm);  in VRgather_vi()
4035 void Riscv64Assembler::VSlideup_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSlideup_vx()  argument
4037   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSlideup_vx()
4039   const uint32_t funct7 = EncodeRVVF7(0b001110, vm);  in VSlideup_vx()
4043 void Riscv64Assembler::VSlideup_vi(VRegister vd, VRegister vs2, uint32_t uimm5, VM vm) {  in VSlideup_vi()  argument
4045   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSlideup_vi()
4047   const uint32_t funct7 = EncodeRVVF7(0b001110, vm);  in VSlideup_vi()
4051 void Riscv64Assembler::VRgatherei16_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VRgatherei16_vv()  argument
4053   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VRgatherei16_vv()
4056   const uint32_t funct7 = EncodeRVVF7(0b001110, vm);  in VRgatherei16_vv()
4060 void Riscv64Assembler::VSlidedown_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSlidedown_vx()  argument
4062   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSlidedown_vx()
4064   const uint32_t funct7 = EncodeRVVF7(0b001111, vm);  in VSlidedown_vx()
4068 void Riscv64Assembler::VSlidedown_vi(VRegister vd, VRegister vs2, uint32_t uimm5, VM vm) {  in VSlidedown_vi()  argument
4070   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSlidedown_vi()
4071   const uint32_t funct7 = EncodeRVVF7(0b001111, vm);  in VSlidedown_vi()
4078   const uint32_t funct7 = EncodeRVVF7(0b010000, VM::kV0_t);  in VAdc_vvm()
4085   const uint32_t funct7 = EncodeRVVF7(0b010000, VM::kV0_t);  in VAdc_vxm()
4092   const uint32_t funct7 = EncodeRVVF7(0b010000, VM::kV0_t);  in VAdc_vim()
4098   const uint32_t funct7 = EncodeRVVF7(0b010001, VM::kV0_t);  in VMadc_vvm()
4104   const uint32_t funct7 = EncodeRVVF7(0b010001, VM::kV0_t);  in VMadc_vxm()
4110   const uint32_t funct7 = EncodeRVVF7(0b010001, VM::kV0_t);  in VMadc_vim()
4116   const uint32_t funct7 = EncodeRVVF7(0b010001, VM::kUnmasked);  in VMadc_vv()
4122   const uint32_t funct7 = EncodeRVVF7(0b010001, VM::kUnmasked);  in VMadc_vx()
4128   const uint32_t funct7 = EncodeRVVF7(0b010001, VM::kUnmasked);  in VMadc_vi()
4135   const uint32_t funct7 = EncodeRVVF7(0b010010, VM::kV0_t);  in VSbc_vvm()
4142   const uint32_t funct7 = EncodeRVVF7(0b010010, VM::kV0_t);  in VSbc_vxm()
4148   const uint32_t funct7 = EncodeRVVF7(0b010011, VM::kV0_t);  in VMsbc_vvm()
4154   const uint32_t funct7 = EncodeRVVF7(0b010011, VM::kV0_t);  in VMsbc_vxm()
4160   const uint32_t funct7 = EncodeRVVF7(0b010011, VM::kUnmasked);  in VMsbc_vv()
4166   const uint32_t funct7 = EncodeRVVF7(0b010011, VM::kUnmasked);  in VMsbc_vx()
4173   const uint32_t funct7 = EncodeRVVF7(0b010111, VM::kV0_t);  in VMerge_vvm()
4180   const uint32_t funct7 = EncodeRVVF7(0b010111, VM::kV0_t);  in VMerge_vxm()
4187   const uint32_t funct7 = EncodeRVVF7(0b010111, VM::kV0_t);  in VMerge_vim()
4193   const uint32_t funct7 = EncodeRVVF7(0b010111, VM::kUnmasked);  in VMv_vv()
4199   const uint32_t funct7 = EncodeRVVF7(0b010111, VM::kUnmasked);  in VMv_vx()
4205   const uint32_t funct7 = EncodeRVVF7(0b010111, VM::kUnmasked);  in VMv_vi()
4209 void Riscv64Assembler::VMseq_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VMseq_vv()  argument
4211   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMseq_vv()
4212   const uint32_t funct7 = EncodeRVVF7(0b011000, vm);  in VMseq_vv()
4216 void Riscv64Assembler::VMseq_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMseq_vx()  argument
4218   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMseq_vx()
4219   const uint32_t funct7 = EncodeRVVF7(0b011000, vm);  in VMseq_vx()
4223 void Riscv64Assembler::VMseq_vi(VRegister vd, VRegister vs2, int32_t imm5, VM vm) {  in VMseq_vi()  argument
4225   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMseq_vi()
4226   const uint32_t funct7 = EncodeRVVF7(0b011000, vm);  in VMseq_vi()
4230 void Riscv64Assembler::VMsne_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VMsne_vv()  argument
4232   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMsne_vv()
4233   const uint32_t funct7 = EncodeRVVF7(0b011001, vm);  in VMsne_vv()
4237 void Riscv64Assembler::VMsne_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMsne_vx()  argument
4239   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMsne_vx()
4240   const uint32_t funct7 = EncodeRVVF7(0b011001, vm);  in VMsne_vx()
4244 void Riscv64Assembler::VMsne_vi(VRegister vd, VRegister vs2, int32_t imm5, VM vm) {  in VMsne_vi()  argument
4246   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMsne_vi()
4247   const uint32_t funct7 = EncodeRVVF7(0b011001, vm);  in VMsne_vi()
4251 void Riscv64Assembler::VMsltu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VMsltu_vv()  argument
4253   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMsltu_vv()
4254   const uint32_t funct7 = EncodeRVVF7(0b011010, vm);  in VMsltu_vv()
4258 void Riscv64Assembler::VMsltu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMsltu_vx()  argument
4260   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMsltu_vx()
4261   const uint32_t funct7 = EncodeRVVF7(0b011010, vm);  in VMsltu_vx()
4265 void Riscv64Assembler::VMsgtu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VMsgtu_vv()  argument
4267   VMsltu_vv(vd, vs1, vs2, vm);  in VMsgtu_vv()
4270 void Riscv64Assembler::VMslt_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VMslt_vv()  argument
4272   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMslt_vv()
4273   const uint32_t funct7 = EncodeRVVF7(0b011011, vm);  in VMslt_vv()
4277 void Riscv64Assembler::VMslt_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMslt_vx()  argument
4279   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMslt_vx()
4280   const uint32_t funct7 = EncodeRVVF7(0b011011, vm);  in VMslt_vx()
4284 void Riscv64Assembler::VMsgt_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VMsgt_vv()  argument
4285   VMslt_vv(vd, vs1, vs2, vm);  in VMsgt_vv()
4288 void Riscv64Assembler::VMsleu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VMsleu_vv()  argument
4290   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMsleu_vv()
4291   const uint32_t funct7 = EncodeRVVF7(0b011100, vm);  in VMsleu_vv()
4295 void Riscv64Assembler::VMsleu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMsleu_vx()  argument
4297   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMsleu_vx()
4298   const uint32_t funct7 = EncodeRVVF7(0b011100, vm);  in VMsleu_vx()
4302 void Riscv64Assembler::VMsleu_vi(VRegister vd, VRegister vs2, int32_t imm5, VM vm) {  in VMsleu_vi()  argument
4304   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMsleu_vi()
4305   const uint32_t funct7 = EncodeRVVF7(0b011100, vm);  in VMsleu_vi()
4309 void Riscv64Assembler::VMsgeu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VMsgeu_vv()  argument
4310   VMsleu_vv(vd, vs1, vs2, vm);  in VMsgeu_vv()
4313 void Riscv64Assembler::VMsltu_vi(VRegister vd, VRegister vs2, int32_t aimm5, VM vm) {  in VMsltu_vi()  argument
4315   VMsleu_vi(vd, vs2, aimm5 - 1, vm);  in VMsltu_vi()
4318 void Riscv64Assembler::VMsle_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VMsle_vv()  argument
4320   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMsle_vv()
4321   const uint32_t funct7 = EncodeRVVF7(0b011101, vm);  in VMsle_vv()
4325 void Riscv64Assembler::VMsle_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMsle_vx()  argument
4327   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMsle_vx()
4328   const uint32_t funct7 = EncodeRVVF7(0b011101, vm);  in VMsle_vx()
4332 void Riscv64Assembler::VMsle_vi(VRegister vd, VRegister vs2, int32_t imm5, VM vm) {  in VMsle_vi()  argument
4334   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMsle_vi()
4335   const uint32_t funct7 = EncodeRVVF7(0b011101, vm);  in VMsle_vi()
4339 void Riscv64Assembler::VMsge_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VMsge_vv()  argument
4340   VMsle_vv(vd, vs1, vs2, vm);  in VMsge_vv()
4343 void Riscv64Assembler::VMslt_vi(VRegister vd, VRegister vs2, int32_t aimm5, VM vm) {  in VMslt_vi()  argument
4344   VMsle_vi(vd, vs2, aimm5 - 1, vm);  in VMslt_vi()
4347 void Riscv64Assembler::VMsgtu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMsgtu_vx()  argument
4349   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMsgtu_vx()
4350   const uint32_t funct7 = EncodeRVVF7(0b011110, vm);  in VMsgtu_vx()
4354 void Riscv64Assembler::VMsgtu_vi(VRegister vd, VRegister vs2, int32_t imm5, VM vm) {  in VMsgtu_vi()  argument
4356   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMsgtu_vi()
4357   const uint32_t funct7 = EncodeRVVF7(0b011110, vm);  in VMsgtu_vi()
4361 void Riscv64Assembler::VMsgeu_vi(VRegister vd, VRegister vs2, int32_t aimm5, VM vm) {  in VMsgeu_vi()  argument
4364   VMsgtu_vi(vd, vs2, aimm5 - 1, vm);  in VMsgeu_vi()
4367 void Riscv64Assembler::VMsgt_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMsgt_vx()  argument
4369   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMsgt_vx()
4370   const uint32_t funct7 = EncodeRVVF7(0b011111, vm);  in VMsgt_vx()
4374 void Riscv64Assembler::VMsgt_vi(VRegister vd, VRegister vs2, int32_t imm5, VM vm) {  in VMsgt_vi()  argument
4376   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMsgt_vi()
4377   const uint32_t funct7 = EncodeRVVF7(0b011111, vm);  in VMsgt_vi()
4381 void Riscv64Assembler::VMsge_vi(VRegister vd, VRegister vs2, int32_t aimm5, VM vm) {  in VMsge_vi()  argument
4382   VMsgt_vi(vd, vs2, aimm5 - 1, vm);  in VMsge_vi()
4385 void Riscv64Assembler::VSaddu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VSaddu_vv()  argument
4387   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSaddu_vv()
4388   const uint32_t funct7 = EncodeRVVF7(0b100000, vm);  in VSaddu_vv()
4392 void Riscv64Assembler::VSaddu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSaddu_vx()  argument
4394   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSaddu_vx()
4395   const uint32_t funct7 = EncodeRVVF7(0b100000, vm);  in VSaddu_vx()
4399 void Riscv64Assembler::VSaddu_vi(VRegister vd, VRegister vs2, int32_t imm5, VM vm) {  in VSaddu_vi()  argument
4401   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSaddu_vi()
4402   const uint32_t funct7 = EncodeRVVF7(0b100000, vm);  in VSaddu_vi()
4406 void Riscv64Assembler::VSadd_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VSadd_vv()  argument
4408   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSadd_vv()
4409   const uint32_t funct7 = EncodeRVVF7(0b100001, vm);  in VSadd_vv()
4413 void Riscv64Assembler::VSadd_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSadd_vx()  argument
4415   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSadd_vx()
4416   const uint32_t funct7 = EncodeRVVF7(0b100001, vm);  in VSadd_vx()
4420 void Riscv64Assembler::VSadd_vi(VRegister vd, VRegister vs2, int32_t imm5, VM vm) {  in VSadd_vi()  argument
4422   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSadd_vi()
4423   const uint32_t funct7 = EncodeRVVF7(0b100001, vm);  in VSadd_vi()
4427 void Riscv64Assembler::VSsubu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VSsubu_vv()  argument
4429   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSsubu_vv()
4430   const uint32_t funct7 = EncodeRVVF7(0b100010, vm);  in VSsubu_vv()
4434 void Riscv64Assembler::VSsubu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSsubu_vx()  argument
4436   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSsubu_vx()
4437   const uint32_t funct7 = EncodeRVVF7(0b100010, vm);  in VSsubu_vx()
4441 void Riscv64Assembler::VSsub_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VSsub_vv()  argument
4443   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSsub_vv()
4444   const uint32_t funct7 = EncodeRVVF7(0b100011, vm);  in VSsub_vv()
4448 void Riscv64Assembler::VSsub_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSsub_vx()  argument
4450   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSsub_vx()
4451   const uint32_t funct7 = EncodeRVVF7(0b100011, vm);  in VSsub_vx()
4455 void Riscv64Assembler::VSll_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VSll_vv()  argument
4457   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSll_vv()
4458   const uint32_t funct7 = EncodeRVVF7(0b100101, vm);  in VSll_vv()
4462 void Riscv64Assembler::VSll_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSll_vx()  argument
4464   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSll_vx()
4465   const uint32_t funct7 = EncodeRVVF7(0b100101, vm);  in VSll_vx()
4469 void Riscv64Assembler::VSll_vi(VRegister vd, VRegister vs2, uint32_t uimm5, VM vm) {  in VSll_vi()  argument
4471   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSll_vi()
4472   const uint32_t funct7 = EncodeRVVF7(0b100101, vm);  in VSll_vi()
4476 void Riscv64Assembler::VSmul_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VSmul_vv()  argument
4478   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSmul_vv()
4479   const uint32_t funct7 = EncodeRVVF7(0b100111, vm);  in VSmul_vv()
4483 void Riscv64Assembler::VSmul_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSmul_vx()  argument
4485   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSmul_vx()
4486   const uint32_t funct7 = EncodeRVVF7(0b100111, vm);  in VSmul_vx()
4492   const uint32_t funct7 = EncodeRVVF7(0b100111, VM::kUnmasked);  in Vmv1r_v()
4501   const uint32_t funct7 = EncodeRVVF7(0b100111, VM::kUnmasked);  in Vmv2r_v()
4510   const uint32_t funct7 = EncodeRVVF7(0b100111, VM::kUnmasked);  in Vmv4r_v()
4519   const uint32_t funct7 = EncodeRVVF7(0b100111, VM::kUnmasked);  in Vmv8r_v()
4524 void Riscv64Assembler::VSrl_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VSrl_vv()  argument
4526   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSrl_vv()
4527   const uint32_t funct7 = EncodeRVVF7(0b101000, vm);  in VSrl_vv()
4531 void Riscv64Assembler::VSrl_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSrl_vx()  argument
4533   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSrl_vx()
4534   const uint32_t funct7 = EncodeRVVF7(0b101000, vm);  in VSrl_vx()
4538 void Riscv64Assembler::VSrl_vi(VRegister vd, VRegister vs2, uint32_t uimm5, VM vm) {  in VSrl_vi()  argument
4540   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSrl_vi()
4541   const uint32_t funct7 = EncodeRVVF7(0b101000, vm);  in VSrl_vi()
4545 void Riscv64Assembler::VSra_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VSra_vv()  argument
4547   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSra_vv()
4548   const uint32_t funct7 = EncodeRVVF7(0b101001, vm);  in VSra_vv()
4552 void Riscv64Assembler::VSra_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSra_vx()  argument
4554   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSra_vx()
4555   const uint32_t funct7 = EncodeRVVF7(0b101001, vm);  in VSra_vx()
4559 void Riscv64Assembler::VSra_vi(VRegister vd, VRegister vs2, uint32_t uimm5, VM vm) {  in VSra_vi()  argument
4561   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSra_vi()
4562   const uint32_t funct7 = EncodeRVVF7(0b101001, vm);  in VSra_vi()
4566 void Riscv64Assembler::VSsrl_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VSsrl_vv()  argument
4568   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSsrl_vv()
4569   const uint32_t funct7 = EncodeRVVF7(0b101010, vm);  in VSsrl_vv()
4573 void Riscv64Assembler::VSsrl_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSsrl_vx()  argument
4575   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSsrl_vx()
4576   const uint32_t funct7 = EncodeRVVF7(0b101010, vm);  in VSsrl_vx()
4580 void Riscv64Assembler::VSsrl_vi(VRegister vd, VRegister vs2, uint32_t uimm5, VM vm) {  in VSsrl_vi()  argument
4582   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSsrl_vi()
4583   const uint32_t funct7 = EncodeRVVF7(0b101010, vm);  in VSsrl_vi()
4587 void Riscv64Assembler::VSsra_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VSsra_vv()  argument
4589   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSsra_vv()
4590   const uint32_t funct7 = EncodeRVVF7(0b101011, vm);  in VSsra_vv()
4594 void Riscv64Assembler::VSsra_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSsra_vx()  argument
4596   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSsra_vx()
4597   const uint32_t funct7 = EncodeRVVF7(0b101011, vm);  in VSsra_vx()
4601 void Riscv64Assembler::VSsra_vi(VRegister vd, VRegister vs2, uint32_t uimm5, VM vm) {  in VSsra_vi()  argument
4603   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSsra_vi()
4604   const uint32_t funct7 = EncodeRVVF7(0b101011, vm);  in VSsra_vi()
4608 void Riscv64Assembler::VNsrl_wv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VNsrl_wv()  argument
4610   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VNsrl_wv()
4611   const uint32_t funct7 = EncodeRVVF7(0b101100, vm);  in VNsrl_wv()
4615 void Riscv64Assembler::VNsrl_wx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VNsrl_wx()  argument
4617   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VNsrl_wx()
4618   const uint32_t funct7 = EncodeRVVF7(0b101100, vm);  in VNsrl_wx()
4622 void Riscv64Assembler::VNsrl_wi(VRegister vd, VRegister vs2, uint32_t uimm5, VM vm) {  in VNsrl_wi()  argument
4624   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VNsrl_wi()
4625   const uint32_t funct7 = EncodeRVVF7(0b101100, vm);  in VNsrl_wi()
4629 void Riscv64Assembler::VNcvt_x_x_w(VRegister vd, VRegister vs2, VM vm) {  in VNcvt_x_x_w()  argument
4631   VNsrl_wx(vd, vs2, Zero, vm);  in VNcvt_x_x_w()
4634 void Riscv64Assembler::VNsra_wv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VNsra_wv()  argument
4636   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VNsra_wv()
4637   const uint32_t funct7 = EncodeRVVF7(0b101101, vm);  in VNsra_wv()
4641 void Riscv64Assembler::VNsra_wx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VNsra_wx()  argument
4643   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VNsra_wx()
4644   const uint32_t funct7 = EncodeRVVF7(0b101101, vm);  in VNsra_wx()
4648 void Riscv64Assembler::VNsra_wi(VRegister vd, VRegister vs2, uint32_t uimm5, VM vm) {  in VNsra_wi()  argument
4650   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VNsra_wi()
4651   const uint32_t funct7 = EncodeRVVF7(0b101101, vm);  in VNsra_wi()
4655 void Riscv64Assembler::VNclipu_wv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VNclipu_wv()  argument
4657   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VNclipu_wv()
4658   const uint32_t funct7 = EncodeRVVF7(0b101110, vm);  in VNclipu_wv()
4662 void Riscv64Assembler::VNclipu_wx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VNclipu_wx()  argument
4664   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VNclipu_wx()
4665   const uint32_t funct7 = EncodeRVVF7(0b101110, vm);  in VNclipu_wx()
4669 void Riscv64Assembler::VNclipu_wi(VRegister vd, VRegister vs2, uint32_t uimm5, VM vm) {  in VNclipu_wi()  argument
4671   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VNclipu_wi()
4672   const uint32_t funct7 = EncodeRVVF7(0b101110, vm);  in VNclipu_wi()
4676 void Riscv64Assembler::VNclip_wv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VNclip_wv()  argument
4678   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VNclip_wv()
4679   const uint32_t funct7 = EncodeRVVF7(0b101111, vm);  in VNclip_wv()
4683 void Riscv64Assembler::VNclip_wx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VNclip_wx()  argument
4685   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VNclip_wx()
4686   const uint32_t funct7 = EncodeRVVF7(0b101111, vm);  in VNclip_wx()
4690 void Riscv64Assembler::VNclip_wi(VRegister vd, VRegister vs2, uint32_t uimm5, VM vm) {  in VNclip_wi()  argument
4692   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VNclip_wi()
4693   const uint32_t funct7 = EncodeRVVF7(0b101111, vm);  in VNclip_wi()
4697 void Riscv64Assembler::VWredsumu_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VWredsumu_vs()  argument
4699   const uint32_t funct7 = EncodeRVVF7(0b110000, vm);  in VWredsumu_vs()
4703 void Riscv64Assembler::VWredsum_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VWredsum_vs()  argument
4705   const uint32_t funct7 = EncodeRVVF7(0b110001, vm);  in VWredsum_vs()
4709 void Riscv64Assembler::VRedsum_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VRedsum_vs()  argument
4711   const uint32_t funct7 = EncodeRVVF7(0b000000, vm);  in VRedsum_vs()
4715 void Riscv64Assembler::VRedand_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VRedand_vs()  argument
4717   const uint32_t funct7 = EncodeRVVF7(0b000001, vm);  in VRedand_vs()
4721 void Riscv64Assembler::VRedor_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VRedor_vs()  argument
4723   const uint32_t funct7 = EncodeRVVF7(0b000010, vm);  in VRedor_vs()
4727 void Riscv64Assembler::VRedxor_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VRedxor_vs()  argument
4729   const uint32_t funct7 = EncodeRVVF7(0b000011, vm);  in VRedxor_vs()
4733 void Riscv64Assembler::VRedminu_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VRedminu_vs()  argument
4735   const uint32_t funct7 = EncodeRVVF7(0b000100, vm);  in VRedminu_vs()
4739 void Riscv64Assembler::VRedmin_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VRedmin_vs()  argument
4741   const uint32_t funct7 = EncodeRVVF7(0b000101, vm);  in VRedmin_vs()
4745 void Riscv64Assembler::VRedmaxu_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VRedmaxu_vs()  argument
4747   const uint32_t funct7 = EncodeRVVF7(0b000110, vm);  in VRedmaxu_vs()
4751 void Riscv64Assembler::VRedmax_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VRedmax_vs()  argument
4753   const uint32_t funct7 = EncodeRVVF7(0b000111, vm);  in VRedmax_vs()
4757 void Riscv64Assembler::VAaddu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VAaddu_vv()  argument
4759   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VAaddu_vv()
4760   const uint32_t funct7 = EncodeRVVF7(0b001000, vm);  in VAaddu_vv()
4764 void Riscv64Assembler::VAaddu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VAaddu_vx()  argument
4766   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VAaddu_vx()
4767   const uint32_t funct7 = EncodeRVVF7(0b001000, vm);  in VAaddu_vx()
4771 void Riscv64Assembler::VAadd_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VAadd_vv()  argument
4773   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VAadd_vv()
4774   const uint32_t funct7 = EncodeRVVF7(0b001001, vm);  in VAadd_vv()
4778 void Riscv64Assembler::VAadd_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VAadd_vx()  argument
4780   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VAadd_vx()
4781   const uint32_t funct7 = EncodeRVVF7(0b001001, vm);  in VAadd_vx()
4785 void Riscv64Assembler::VAsubu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VAsubu_vv()  argument
4787   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VAsubu_vv()
4788   const uint32_t funct7 = EncodeRVVF7(0b001010, vm);  in VAsubu_vv()
4792 void Riscv64Assembler::VAsubu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VAsubu_vx()  argument
4794   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VAsubu_vx()
4795   const uint32_t funct7 = EncodeRVVF7(0b001010, vm);  in VAsubu_vx()
4799 void Riscv64Assembler::VAsub_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VAsub_vv()  argument
4801   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VAsub_vv()
4802   const uint32_t funct7 = EncodeRVVF7(0b001011, vm);  in VAsub_vv()
4806 void Riscv64Assembler::VAsub_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VAsub_vx()  argument
4808   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VAsub_vx()
4809   const uint32_t funct7 = EncodeRVVF7(0b001011, vm);  in VAsub_vx()
4813 void Riscv64Assembler::VSlide1up_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSlide1up_vx()  argument
4815   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSlide1up_vx()
4817   const uint32_t funct7 = EncodeRVVF7(0b001110, vm);  in VSlide1up_vx()
4821 void Riscv64Assembler::VSlide1down_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VSlide1down_vx()  argument
4823   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSlide1down_vx()
4824   const uint32_t funct7 = EncodeRVVF7(0b001111, vm);  in VSlide1down_vx()
4832   const uint32_t funct7 = EncodeRVVF7(0b010111, VM::kUnmasked);  in VCompress_vm()
4838   const uint32_t funct7 = EncodeRVVF7(0b011000, VM::kUnmasked);  in VMandn_mm()
4844   const uint32_t funct7 = EncodeRVVF7(0b011001, VM::kUnmasked);  in VMand_mm()
4852   const uint32_t funct7 = EncodeRVVF7(0b011010, VM::kUnmasked);  in VMor_mm()
4858   const uint32_t funct7 = EncodeRVVF7(0b011011, VM::kUnmasked);  in VMxor_mm()
4866   const uint32_t funct7 = EncodeRVVF7(0b011100, VM::kUnmasked);  in VMorn_mm()
4872   const uint32_t funct7 = EncodeRVVF7(0b011101, VM::kUnmasked);  in VMnand_mm()
4880   const uint32_t funct7 = EncodeRVVF7(0b011110, VM::kUnmasked);  in VMnor_mm()
4886   const uint32_t funct7 = EncodeRVVF7(0b011111, VM::kUnmasked);  in VMxnor_mm()
4892 void Riscv64Assembler::VDivu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VDivu_vv()  argument
4894   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VDivu_vv()
4895   const uint32_t funct7 = EncodeRVVF7(0b100000, vm);  in VDivu_vv()
4899 void Riscv64Assembler::VDivu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VDivu_vx()  argument
4901   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VDivu_vx()
4902   const uint32_t funct7 = EncodeRVVF7(0b100000, vm);  in VDivu_vx()
4906 void Riscv64Assembler::VDiv_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VDiv_vv()  argument
4908   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VDiv_vv()
4909   const uint32_t funct7 = EncodeRVVF7(0b100001, vm);  in VDiv_vv()
4913 void Riscv64Assembler::VDiv_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VDiv_vx()  argument
4915   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VDiv_vx()
4916   const uint32_t funct7 = EncodeRVVF7(0b100001, vm);  in VDiv_vx()
4920 void Riscv64Assembler::VRemu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VRemu_vv()  argument
4922   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VRemu_vv()
4923   const uint32_t funct7 = EncodeRVVF7(0b100010, vm);  in VRemu_vv()
4927 void Riscv64Assembler::VRemu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VRemu_vx()  argument
4929   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VRemu_vx()
4930   const uint32_t funct7 = EncodeRVVF7(0b100010, vm);  in VRemu_vx()
4934 void Riscv64Assembler::VRem_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VRem_vv()  argument
4936   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VRem_vv()
4937   const uint32_t funct7 = EncodeRVVF7(0b100011, vm);  in VRem_vv()
4941 void Riscv64Assembler::VRem_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VRem_vx()  argument
4943   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VRem_vx()
4944   const uint32_t funct7 = EncodeRVVF7(0b100011, vm);  in VRem_vx()
4948 void Riscv64Assembler::VMulhu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VMulhu_vv()  argument
4950   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMulhu_vv()
4951   const uint32_t funct7 = EncodeRVVF7(0b100100, vm);  in VMulhu_vv()
4955 void Riscv64Assembler::VMulhu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMulhu_vx()  argument
4957   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMulhu_vx()
4958   const uint32_t funct7 = EncodeRVVF7(0b100100, vm);  in VMulhu_vx()
4962 void Riscv64Assembler::VMul_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VMul_vv()  argument
4964   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMul_vv()
4965   const uint32_t funct7 = EncodeRVVF7(0b100101, vm);  in VMul_vv()
4969 void Riscv64Assembler::VMul_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMul_vx()  argument
4971   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMul_vx()
4972   const uint32_t funct7 = EncodeRVVF7(0b100101, vm);  in VMul_vx()
4976 void Riscv64Assembler::VMulhsu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VMulhsu_vv()  argument
4978   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMulhsu_vv()
4979   const uint32_t funct7 = EncodeRVVF7(0b100110, vm);  in VMulhsu_vv()
4983 void Riscv64Assembler::VMulhsu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMulhsu_vx()  argument
4985   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMulhsu_vx()
4986   const uint32_t funct7 = EncodeRVVF7(0b100110, vm);  in VMulhsu_vx()
4990 void Riscv64Assembler::VMulh_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VMulh_vv()  argument
4992   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMulh_vv()
4993   const uint32_t funct7 = EncodeRVVF7(0b100111, vm);  in VMulh_vv()
4997 void Riscv64Assembler::VMulh_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VMulh_vx()  argument
4999   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMulh_vx()
5000   const uint32_t funct7 = EncodeRVVF7(0b100111, vm);  in VMulh_vx()
5004 void Riscv64Assembler::VMadd_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) {  in VMadd_vv()  argument
5006   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMadd_vv()
5007   const uint32_t funct7 = EncodeRVVF7(0b101001, vm);  in VMadd_vv()
5011 void Riscv64Assembler::VMadd_vx(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VMadd_vx()  argument
5013   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMadd_vx()
5014   const uint32_t funct7 = EncodeRVVF7(0b101001, vm);  in VMadd_vx()
5018 void Riscv64Assembler::VNmsub_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) {  in VNmsub_vv()  argument
5020   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VNmsub_vv()
5021   const uint32_t funct7 = EncodeRVVF7(0b101011, vm);  in VNmsub_vv()
5025 void Riscv64Assembler::VNmsub_vx(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VNmsub_vx()  argument
5027   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VNmsub_vx()
5028   const uint32_t funct7 = EncodeRVVF7(0b101011, vm);  in VNmsub_vx()
5032 void Riscv64Assembler::VMacc_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) {  in VMacc_vv()  argument
5034   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMacc_vv()
5035   const uint32_t funct7 = EncodeRVVF7(0b101101, vm);  in VMacc_vv()
5039 void Riscv64Assembler::VMacc_vx(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VMacc_vx()  argument
5041   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMacc_vx()
5042   const uint32_t funct7 = EncodeRVVF7(0b101101, vm);  in VMacc_vx()
5046 void Riscv64Assembler::VNmsac_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) {  in VNmsac_vv()  argument
5048   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VNmsac_vv()
5051   const uint32_t funct7 = EncodeRVVF7(0b101111, vm);  in VNmsac_vv()
5055 void Riscv64Assembler::VNmsac_vx(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VNmsac_vx()  argument
5057   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VNmsac_vx()
5058   const uint32_t funct7 = EncodeRVVF7(0b101111, vm);  in VNmsac_vx()
5062 void Riscv64Assembler::VWaddu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VWaddu_vv()  argument
5064   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWaddu_vv()
5067   const uint32_t funct7 = EncodeRVVF7(0b110000, vm);  in VWaddu_vv()
5071 void Riscv64Assembler::VWaddu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VWaddu_vx()  argument
5073   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWaddu_vx()
5075   const uint32_t funct7 = EncodeRVVF7(0b110000, vm);  in VWaddu_vx()
5079 void Riscv64Assembler::VWcvtu_x_x_v(VRegister vd, VRegister vs, VM vm) {  in VWcvtu_x_x_v()  argument
5080   VWaddu_vx(vd, vs, Zero, vm);  in VWcvtu_x_x_v()
5083 void Riscv64Assembler::VWadd_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VWadd_vv()  argument
5085   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWadd_vv()
5088   const uint32_t funct7 = EncodeRVVF7(0b110001, vm);  in VWadd_vv()
5092 void Riscv64Assembler::VWadd_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VWadd_vx()  argument
5094   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWadd_vx()
5096   const uint32_t funct7 = EncodeRVVF7(0b110001, vm);  in VWadd_vx()
5100 void Riscv64Assembler::VWcvt_x_x_v(VRegister vd, VRegister vs, VM vm) {  in VWcvt_x_x_v()  argument
5101   VWadd_vx(vd, vs, Zero, vm);  in VWcvt_x_x_v()
5104 void Riscv64Assembler::VWsubu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VWsubu_vv()  argument
5106   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWsubu_vv()
5109   const uint32_t funct7 = EncodeRVVF7(0b110010, vm);  in VWsubu_vv()
5113 void Riscv64Assembler::VWsubu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VWsubu_vx()  argument
5115   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWsubu_vx()
5117   const uint32_t funct7 = EncodeRVVF7(0b110010, vm);  in VWsubu_vx()
5121 void Riscv64Assembler::VWsub_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VWsub_vv()  argument
5123   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWsub_vv()
5126   const uint32_t funct7 = EncodeRVVF7(0b110011, vm);  in VWsub_vv()
5130 void Riscv64Assembler::VWsub_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VWsub_vx()  argument
5132   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWsub_vx()
5134   const uint32_t funct7 = EncodeRVVF7(0b110011, vm);  in VWsub_vx()
5138 void Riscv64Assembler::VWaddu_wv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VWaddu_wv()  argument
5140   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWaddu_wv()
5142   const uint32_t funct7 = EncodeRVVF7(0b110100, vm);  in VWaddu_wv()
5146 void Riscv64Assembler::VWaddu_wx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VWaddu_wx()  argument
5148   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWaddu_wx()
5149   const uint32_t funct7 = EncodeRVVF7(0b110100, vm);  in VWaddu_wx()
5153 void Riscv64Assembler::VWadd_wv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VWadd_wv()  argument
5155   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWadd_wv()
5157   const uint32_t funct7 = EncodeRVVF7(0b110101, vm);  in VWadd_wv()
5161 void Riscv64Assembler::VWadd_wx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VWadd_wx()  argument
5163   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWadd_wx()
5164   const uint32_t funct7 = EncodeRVVF7(0b110101, vm);  in VWadd_wx()
5168 void Riscv64Assembler::VWsubu_wv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VWsubu_wv()  argument
5170   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWsubu_wv()
5172   const uint32_t funct7 = EncodeRVVF7(0b110110, vm);  in VWsubu_wv()
5176 void Riscv64Assembler::VWsubu_wx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VWsubu_wx()  argument
5178   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWsubu_wx()
5179   const uint32_t funct7 = EncodeRVVF7(0b110110, vm);  in VWsubu_wx()
5183 void Riscv64Assembler::VWsub_wv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VWsub_wv()  argument
5185   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWsub_wv()
5187   const uint32_t funct7 = EncodeRVVF7(0b110111, vm);  in VWsub_wv()
5191 void Riscv64Assembler::VWsub_wx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VWsub_wx()  argument
5193   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWsub_wx()
5194   const uint32_t funct7 = EncodeRVVF7(0b110111, vm);  in VWsub_wx()
5198 void Riscv64Assembler::VWmulu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VWmulu_vv()  argument
5200   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWmulu_vv()
5203   const uint32_t funct7 = EncodeRVVF7(0b111000, vm);  in VWmulu_vv()
5207 void Riscv64Assembler::VWmulu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VWmulu_vx()  argument
5209   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWmulu_vx()
5211   const uint32_t funct7 = EncodeRVVF7(0b111000, vm);  in VWmulu_vx()
5215 void Riscv64Assembler::VWmulsu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VWmulsu_vv()  argument
5217   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWmulsu_vv()
5220   const uint32_t funct7 = EncodeRVVF7(0b111010, vm);  in VWmulsu_vv()
5224 void Riscv64Assembler::VWmulsu_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VWmulsu_vx()  argument
5226   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWmulsu_vx()
5228   const uint32_t funct7 = EncodeRVVF7(0b111010, vm);  in VWmulsu_vx()
5232 void Riscv64Assembler::VWmul_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VWmul_vv()  argument
5234   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWmul_vv()
5237   const uint32_t funct7 = EncodeRVVF7(0b111011, vm);  in VWmul_vv()
5241 void Riscv64Assembler::VWmul_vx(VRegister vd, VRegister vs2, XRegister rs1, VM vm) {  in VWmul_vx()  argument
5243   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWmul_vx()
5245   const uint32_t funct7 = EncodeRVVF7(0b111011, vm);  in VWmul_vx()
5249 void Riscv64Assembler::VWmaccu_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) {  in VWmaccu_vv()  argument
5251   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWmaccu_vv()
5254   const uint32_t funct7 = EncodeRVVF7(0b111100, vm);  in VWmaccu_vv()
5258 void Riscv64Assembler::VWmaccu_vx(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VWmaccu_vx()  argument
5260   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWmaccu_vx()
5262   const uint32_t funct7 = EncodeRVVF7(0b111100, vm);  in VWmaccu_vx()
5266 void Riscv64Assembler::VWmacc_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) {  in VWmacc_vv()  argument
5268   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWmacc_vv()
5271   const uint32_t funct7 = EncodeRVVF7(0b111101, vm);  in VWmacc_vv()
5275 void Riscv64Assembler::VWmacc_vx(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VWmacc_vx()  argument
5277   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWmacc_vx()
5279   const uint32_t funct7 = EncodeRVVF7(0b111101, vm);  in VWmacc_vx()
5283 void Riscv64Assembler::VWmaccus_vx(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VWmaccus_vx()  argument
5285   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWmaccus_vx()
5287   const uint32_t funct7 = EncodeRVVF7(0b111110, vm);  in VWmaccus_vx()
5291 void Riscv64Assembler::VWmaccsu_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) {  in VWmaccsu_vv()  argument
5293   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWmaccsu_vv()
5296   const uint32_t funct7 = EncodeRVVF7(0b111111, vm);  in VWmaccsu_vv()
5300 void Riscv64Assembler::VWmaccsu_vx(VRegister vd, XRegister rs1, VRegister vs2, VM vm) {  in VWmaccsu_vx()  argument
5302   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VWmaccsu_vx()
5304   const uint32_t funct7 = EncodeRVVF7(0b111111, vm);  in VWmaccsu_vx()
5308 void Riscv64Assembler::VFadd_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VFadd_vv()  argument
5310   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFadd_vv()
5311   const uint32_t funct7 = EncodeRVVF7(0b000000, vm);  in VFadd_vv()
5315 void Riscv64Assembler::VFadd_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) {  in VFadd_vf()  argument
5317   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFadd_vf()
5318   const uint32_t funct7 = EncodeRVVF7(0b000000, vm);  in VFadd_vf()
5322 void Riscv64Assembler::VFredusum_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VFredusum_vs()  argument
5324   const uint32_t funct7 = EncodeRVVF7(0b000001, vm);  in VFredusum_vs()
5328 void Riscv64Assembler::VFsub_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VFsub_vv()  argument
5330   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFsub_vv()
5331   const uint32_t funct7 = EncodeRVVF7(0b000010, vm);  in VFsub_vv()
5335 void Riscv64Assembler::VFsub_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) {  in VFsub_vf()  argument
5337   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFsub_vf()
5338   const uint32_t funct7 = EncodeRVVF7(0b000010, vm);  in VFsub_vf()
5342 void Riscv64Assembler::VFredosum_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VFredosum_vs()  argument
5344   const uint32_t funct7 = EncodeRVVF7(0b000011, vm);  in VFredosum_vs()
5348 void Riscv64Assembler::VFmin_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VFmin_vv()  argument
5350   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFmin_vv()
5351   const uint32_t funct7 = EncodeRVVF7(0b000100, vm);  in VFmin_vv()
5355 void Riscv64Assembler::VFmin_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) {  in VFmin_vf()  argument
5357   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFmin_vf()
5358   const uint32_t funct7 = EncodeRVVF7(0b000100, vm);  in VFmin_vf()
5362 void Riscv64Assembler::VFredmin_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VFredmin_vs()  argument
5364   const uint32_t funct7 = EncodeRVVF7(0b000101, vm);  in VFredmin_vs()
5368 void Riscv64Assembler::VFmax_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VFmax_vv()  argument
5370   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFmax_vv()
5371   const uint32_t funct7 = EncodeRVVF7(0b000110, vm);  in VFmax_vv()
5375 void Riscv64Assembler::VFmax_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) {  in VFmax_vf()  argument
5377   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFmax_vf()
5378   const uint32_t funct7 = EncodeRVVF7(0b000110, vm);  in VFmax_vf()
5382 void Riscv64Assembler::VFredmax_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VFredmax_vs()  argument
5384   const uint32_t funct7 = EncodeRVVF7(0b000111, vm);  in VFredmax_vs()
5388 void Riscv64Assembler::VFsgnj_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VFsgnj_vv()  argument
5390   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFsgnj_vv()
5391   const uint32_t funct7 = EncodeRVVF7(0b001000, vm);  in VFsgnj_vv()
5395 void Riscv64Assembler::VFsgnj_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) {  in VFsgnj_vf()  argument
5397   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFsgnj_vf()
5398   const uint32_t funct7 = EncodeRVVF7(0b001000, vm);  in VFsgnj_vf()
5402 void Riscv64Assembler::VFsgnjn_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VFsgnjn_vv()  argument
5404   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFsgnjn_vv()
5405   const uint32_t funct7 = EncodeRVVF7(0b001001, vm);  in VFsgnjn_vv()
5409 void Riscv64Assembler::VFsgnjn_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) {  in VFsgnjn_vf()  argument
5411   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFsgnjn_vf()
5412   const uint32_t funct7 = EncodeRVVF7(0b001001, vm);  in VFsgnjn_vf()
5418 void Riscv64Assembler::VFsgnjx_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VFsgnjx_vv()  argument
5420   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFsgnjx_vv()
5421   const uint32_t funct7 = EncodeRVVF7(0b001010, vm);  in VFsgnjx_vv()
5425 void Riscv64Assembler::VFsgnjx_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) {  in VFsgnjx_vf()  argument
5427   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFsgnjx_vf()
5428   const uint32_t funct7 = EncodeRVVF7(0b001010, vm);  in VFsgnjx_vf()
5434 void Riscv64Assembler::VFslide1up_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) {  in VFslide1up_vf()  argument
5436   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFslide1up_vf()
5438   const uint32_t funct7 = EncodeRVVF7(0b001110, vm);  in VFslide1up_vf()
5442 void Riscv64Assembler::VFslide1down_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) {  in VFslide1down_vf()  argument
5444   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFslide1down_vf()
5445   const uint32_t funct7 = EncodeRVVF7(0b001111, vm);  in VFslide1down_vf()
5452   const uint32_t funct7 = EncodeRVVF7(0b010111, VM::kV0_t);  in VFmerge_vfm()
5458   const uint32_t funct7 = EncodeRVVF7(0b010111, VM::kUnmasked);  in VFmv_v_f()
5462 void Riscv64Assembler::VMfeq_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VMfeq_vv()  argument
5464   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMfeq_vv()
5465   const uint32_t funct7 = EncodeRVVF7(0b011000, vm);  in VMfeq_vv()
5469 void Riscv64Assembler::VMfeq_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) {  in VMfeq_vf()  argument
5471   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMfeq_vf()
5472   const uint32_t funct7 = EncodeRVVF7(0b011000, vm);  in VMfeq_vf()
5476 void Riscv64Assembler::VMfle_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VMfle_vv()  argument
5478   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMfle_vv()
5479   const uint32_t funct7 = EncodeRVVF7(0b011001, vm);  in VMfle_vv()
5483 void Riscv64Assembler::VMfle_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) {  in VMfle_vf()  argument
5485   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMfle_vf()
5486   const uint32_t funct7 = EncodeRVVF7(0b011001, vm);  in VMfle_vf()
5490 void Riscv64Assembler::VMfge_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VMfge_vv()  argument
5491   VMfle_vv(vd, vs1, vs2, vm);  in VMfge_vv()
5494 void Riscv64Assembler::VMflt_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VMflt_vv()  argument
5496   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMflt_vv()
5497   const uint32_t funct7 = EncodeRVVF7(0b011011, vm);  in VMflt_vv()
5501 void Riscv64Assembler::VMflt_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) {  in VMflt_vf()  argument
5503   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMflt_vf()
5504   const uint32_t funct7 = EncodeRVVF7(0b011011, vm);  in VMflt_vf()
5508 void Riscv64Assembler::VMfgt_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VMfgt_vv()  argument
5509   VMflt_vv(vd, vs1, vs2, vm);  in VMfgt_vv()
5512 void Riscv64Assembler::VMfne_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VMfne_vv()  argument
5514   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMfne_vv()
5515   const uint32_t funct7 = EncodeRVVF7(0b011100, vm);  in VMfne_vv()
5519 void Riscv64Assembler::VMfne_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) {  in VMfne_vf()  argument
5521   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMfne_vf()
5522   const uint32_t funct7 = EncodeRVVF7(0b011100, vm);  in VMfne_vf()
5526 void Riscv64Assembler::VMfgt_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) {  in VMfgt_vf()  argument
5528   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMfgt_vf()
5529   const uint32_t funct7 = EncodeRVVF7(0b011101, vm);  in VMfgt_vf()
5533 void Riscv64Assembler::VMfge_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) {  in VMfge_vf()  argument
5535   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMfge_vf()
5536   const uint32_t funct7 = EncodeRVVF7(0b011111, vm);  in VMfge_vf()
5540 void Riscv64Assembler::VFdiv_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VFdiv_vv()  argument
5542   const uint32_t funct7 = EncodeRVVF7(0b100000, vm);  in VFdiv_vv()
5546 void Riscv64Assembler::VFdiv_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) {  in VFdiv_vf()  argument
5548   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFdiv_vf()
5549   const uint32_t funct7 = EncodeRVVF7(0b100000, vm);  in VFdiv_vf()
5553 void Riscv64Assembler::VFrdiv_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) {  in VFrdiv_vf()  argument
5555   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFrdiv_vf()
5556   const uint32_t funct7 = EncodeRVVF7(0b100001, vm);  in VFrdiv_vf()
5560 void Riscv64Assembler::VFmul_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VFmul_vv()  argument
5562   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFmul_vv()
5563   const uint32_t funct7 = EncodeRVVF7(0b100100, vm);  in VFmul_vv()
5567 void Riscv64Assembler::VFmul_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) {  in VFmul_vf()  argument
5569   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFmul_vf()
5570   const uint32_t funct7 = EncodeRVVF7(0b100100, vm);  in VFmul_vf()
5574 void Riscv64Assembler::VFrsub_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) {  in VFrsub_vf()  argument
5576   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFrsub_vf()
5577   const uint32_t funct7 = EncodeRVVF7(0b100111, vm);  in VFrsub_vf()
5581 void Riscv64Assembler::VFmadd_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) {  in VFmadd_vv()  argument
5583   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFmadd_vv()
5584   const uint32_t funct7 = EncodeRVVF7(0b101000, vm);  in VFmadd_vv()
5588 void Riscv64Assembler::VFmadd_vf(VRegister vd, FRegister fs1, VRegister vs2, VM vm) {  in VFmadd_vf()  argument
5590   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFmadd_vf()
5591   const uint32_t funct7 = EncodeRVVF7(0b101000, vm);  in VFmadd_vf()
5595 void Riscv64Assembler::VFnmadd_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) {  in VFnmadd_vv()  argument
5597   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFnmadd_vv()
5598   const uint32_t funct7 = EncodeRVVF7(0b101001, vm);  in VFnmadd_vv()
5602 void Riscv64Assembler::VFnmadd_vf(VRegister vd, FRegister fs1, VRegister vs2, VM vm) {  in VFnmadd_vf()  argument
5604   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFnmadd_vf()
5605   const uint32_t funct7 = EncodeRVVF7(0b101001, vm);  in VFnmadd_vf()
5609 void Riscv64Assembler::VFmsub_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) {  in VFmsub_vv()  argument
5611   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFmsub_vv()
5612   const uint32_t funct7 = EncodeRVVF7(0b101010, vm);  in VFmsub_vv()
5616 void Riscv64Assembler::VFmsub_vf(VRegister vd, FRegister fs1, VRegister vs2, VM vm) {  in VFmsub_vf()  argument
5618   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFmsub_vf()
5619   const uint32_t funct7 = EncodeRVVF7(0b101010, vm);  in VFmsub_vf()
5623 void Riscv64Assembler::VFnmsub_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) {  in VFnmsub_vv()  argument
5625   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFnmsub_vv()
5626   const uint32_t funct7 = EncodeRVVF7(0b101011, vm);  in VFnmsub_vv()
5630 void Riscv64Assembler::VFnmsub_vf(VRegister vd, FRegister fs1, VRegister vs2, VM vm) {  in VFnmsub_vf()  argument
5632   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFnmsub_vf()
5633   const uint32_t funct7 = EncodeRVVF7(0b101011, vm);  in VFnmsub_vf()
5637 void Riscv64Assembler::VFmacc_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) {  in VFmacc_vv()  argument
5639   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFmacc_vv()
5640   const uint32_t funct7 = EncodeRVVF7(0b101100, vm);  in VFmacc_vv()
5644 void Riscv64Assembler::VFmacc_vf(VRegister vd, FRegister fs1, VRegister vs2, VM vm) {  in VFmacc_vf()  argument
5646   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFmacc_vf()
5647   const uint32_t funct7 = EncodeRVVF7(0b101100, vm);  in VFmacc_vf()
5651 void Riscv64Assembler::VFnmacc_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) {  in VFnmacc_vv()  argument
5653   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFnmacc_vv()
5654   const uint32_t funct7 = EncodeRVVF7(0b101101, vm);  in VFnmacc_vv()
5658 void Riscv64Assembler::VFnmacc_vf(VRegister vd, FRegister fs1, VRegister vs2, VM vm) {  in VFnmacc_vf()  argument
5660   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFnmacc_vf()
5661   const uint32_t funct7 = EncodeRVVF7(0b101101, vm);  in VFnmacc_vf()
5665 void Riscv64Assembler::VFmsac_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) {  in VFmsac_vv()  argument
5667   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFmsac_vv()
5668   const uint32_t funct7 = EncodeRVVF7(0b101110, vm);  in VFmsac_vv()
5672 void Riscv64Assembler::VFmsac_vf(VRegister vd, FRegister fs1, VRegister vs2, VM vm) {  in VFmsac_vf()  argument
5674   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFmsac_vf()
5675   const uint32_t funct7 = EncodeRVVF7(0b101110, vm);  in VFmsac_vf()
5679 void Riscv64Assembler::VFnmsac_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) {  in VFnmsac_vv()  argument
5681   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFnmsac_vv()
5682   const uint32_t funct7 = EncodeRVVF7(0b101111, vm);  in VFnmsac_vv()
5686 void Riscv64Assembler::VFnmsac_vf(VRegister vd, FRegister fs1, VRegister vs2, VM vm) {  in VFnmsac_vf()  argument
5688   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFnmsac_vf()
5689   const uint32_t funct7 = EncodeRVVF7(0b101111, vm);  in VFnmsac_vf()
5693 void Riscv64Assembler::VFwadd_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VFwadd_vv()  argument
5695   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFwadd_vv()
5698   const uint32_t funct7 = EncodeRVVF7(0b110000, vm);  in VFwadd_vv()
5702 void Riscv64Assembler::VFwadd_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) {  in VFwadd_vf()  argument
5704   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFwadd_vf()
5706   const uint32_t funct7 = EncodeRVVF7(0b110000, vm);  in VFwadd_vf()
5710 void Riscv64Assembler::VFwredusum_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VFwredusum_vs()  argument
5712   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFwredusum_vs()
5713   const uint32_t funct7 = EncodeRVVF7(0b110001, vm);  in VFwredusum_vs()
5717 void Riscv64Assembler::VFwsub_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VFwsub_vv()  argument
5719   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFwsub_vv()
5722   const uint32_t funct7 = EncodeRVVF7(0b110010, vm);  in VFwsub_vv()
5726 void Riscv64Assembler::VFwsub_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) {  in VFwsub_vf()  argument
5728   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFwsub_vf()
5730   const uint32_t funct7 = EncodeRVVF7(0b110010, vm);  in VFwsub_vf()
5734 void Riscv64Assembler::VFwredosum_vs(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VFwredosum_vs()  argument
5736   const uint32_t funct7 = EncodeRVVF7(0b110011, vm);  in VFwredosum_vs()
5740 void Riscv64Assembler::VFwadd_wv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VFwadd_wv()  argument
5742   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFwadd_wv()
5744   const uint32_t funct7 = EncodeRVVF7(0b110100, vm);  in VFwadd_wv()
5748 void Riscv64Assembler::VFwadd_wf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) {  in VFwadd_wf()  argument
5750   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFwadd_wf()
5751   const uint32_t funct7 = EncodeRVVF7(0b110100, vm);  in VFwadd_wf()
5755 void Riscv64Assembler::VFwsub_wv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VFwsub_wv()  argument
5757   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFwsub_wv()
5759   const uint32_t funct7 = EncodeRVVF7(0b110110, vm);  in VFwsub_wv()
5763 void Riscv64Assembler::VFwsub_wf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) {  in VFwsub_wf()  argument
5765   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFwsub_wf()
5766   const uint32_t funct7 = EncodeRVVF7(0b110110, vm);  in VFwsub_wf()
5770 void Riscv64Assembler::VFwmul_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) {  in VFwmul_vv()  argument
5772   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFwmul_vv()
5775   const uint32_t funct7 = EncodeRVVF7(0b111000, vm);  in VFwmul_vv()
5779 void Riscv64Assembler::VFwmul_vf(VRegister vd, VRegister vs2, FRegister fs1, VM vm) {  in VFwmul_vf()  argument
5781   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFwmul_vf()
5783   const uint32_t funct7 = EncodeRVVF7(0b111000, vm);  in VFwmul_vf()
5787 void Riscv64Assembler::VFwmacc_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) {  in VFwmacc_vv()  argument
5789   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFwmacc_vv()
5792   const uint32_t funct7 = EncodeRVVF7(0b111100, vm);  in VFwmacc_vv()
5796 void Riscv64Assembler::VFwmacc_vf(VRegister vd, FRegister fs1, VRegister vs2, VM vm) {  in VFwmacc_vf()  argument
5798   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFwmacc_vf()
5800   const uint32_t funct7 = EncodeRVVF7(0b111100, vm);  in VFwmacc_vf()
5804 void Riscv64Assembler::VFwnmacc_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) {  in VFwnmacc_vv()  argument
5806   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFwnmacc_vv()
5809   const uint32_t funct7 = EncodeRVVF7(0b111101, vm);  in VFwnmacc_vv()
5813 void Riscv64Assembler::VFwnmacc_vf(VRegister vd, FRegister fs1, VRegister vs2, VM vm) {  in VFwnmacc_vf()  argument
5815   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFwnmacc_vf()
5817   const uint32_t funct7 = EncodeRVVF7(0b111101, vm);  in VFwnmacc_vf()
5821 void Riscv64Assembler::VFwmsac_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) {  in VFwmsac_vv()  argument
5823   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFwmsac_vv()
5826   const uint32_t funct7 = EncodeRVVF7(0b111110, vm);  in VFwmsac_vv()
5830 void Riscv64Assembler::VFwmsac_vf(VRegister vd, FRegister fs1, VRegister vs2, VM vm) {  in VFwmsac_vf()  argument
5832   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFwmsac_vf()
5834   const uint32_t funct7 = EncodeRVVF7(0b111110, vm);  in VFwmsac_vf()
5838 void Riscv64Assembler::VFwnmsac_vv(VRegister vd, VRegister vs1, VRegister vs2, VM vm) {  in VFwnmsac_vv()  argument
5840   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFwnmsac_vv()
5843   const uint32_t funct7 = EncodeRVVF7(0b111111, vm);  in VFwnmsac_vv()
5847 void Riscv64Assembler::VFwnmsac_vf(VRegister vd, FRegister fs1, VRegister vs2, VM vm) {  in VFwnmsac_vf()  argument
5849   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFwnmsac_vf()
5851   const uint32_t funct7 = EncodeRVVF7(0b111111, vm);  in VFwnmsac_vf()
5857   const uint32_t funct7 = EncodeRVVF7(0b010000, VM::kUnmasked);  in VMv_s_x()
5863   const uint32_t funct7 = EncodeRVVF7(0b010000, VM::kUnmasked);  in VMv_x_s()
5867 void Riscv64Assembler::VCpop_m(XRegister rd, VRegister vs2, VM vm) {  in VCpop_m()  argument
5869   const uint32_t funct7 = EncodeRVVF7(0b010000, vm);  in VCpop_m()
5873 void Riscv64Assembler::VFirst_m(XRegister rd, VRegister vs2, VM vm) {  in VFirst_m()  argument
5875   const uint32_t funct7 = EncodeRVVF7(0b010000, vm);  in VFirst_m()
5879 void Riscv64Assembler::VZext_vf8(VRegister vd, VRegister vs2, VM vm) {  in VZext_vf8()  argument
5881   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VZext_vf8()
5882   const uint32_t funct7 = EncodeRVVF7(0b010010, vm);  in VZext_vf8()
5886 void Riscv64Assembler::VSext_vf8(VRegister vd, VRegister vs2, VM vm) {  in VSext_vf8()  argument
5888   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSext_vf8()
5889   const uint32_t funct7 = EncodeRVVF7(0b010010, vm);  in VSext_vf8()
5893 void Riscv64Assembler::VZext_vf4(VRegister vd, VRegister vs2, VM vm) {  in VZext_vf4()  argument
5895   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VZext_vf4()
5896   const uint32_t funct7 = EncodeRVVF7(0b010010, vm);  in VZext_vf4()
5900 void Riscv64Assembler::VSext_vf4(VRegister vd, VRegister vs2, VM vm) {  in VSext_vf4()  argument
5902   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSext_vf4()
5903   const uint32_t funct7 = EncodeRVVF7(0b010010, vm);  in VSext_vf4()
5907 void Riscv64Assembler::VZext_vf2(VRegister vd, VRegister vs2, VM vm) {  in VZext_vf2()  argument
5909   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VZext_vf2()
5910   const uint32_t funct7 = EncodeRVVF7(0b010010, vm);  in VZext_vf2()
5914 void Riscv64Assembler::VSext_vf2(VRegister vd, VRegister vs2, VM vm) {  in VSext_vf2()  argument
5916   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VSext_vf2()
5917   const uint32_t funct7 = EncodeRVVF7(0b010010, vm);  in VSext_vf2()
5923   const uint32_t funct7 = EncodeRVVF7(0b010000, VM::kUnmasked);  in VFmv_s_f()
5929   const uint32_t funct7 = EncodeRVVF7(0b010000, VM::kUnmasked);  in VFmv_f_s()
5933 void Riscv64Assembler::VFcvt_xu_f_v(VRegister vd, VRegister vs2, VM vm) {  in VFcvt_xu_f_v()  argument
5935   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFcvt_xu_f_v()
5936   const uint32_t funct7 = EncodeRVVF7(0b010010, vm);  in VFcvt_xu_f_v()
5940 void Riscv64Assembler::VFcvt_x_f_v(VRegister vd, VRegister vs2, VM vm) {  in VFcvt_x_f_v()  argument
5942   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFcvt_x_f_v()
5943   const uint32_t funct7 = EncodeRVVF7(0b010010, vm);  in VFcvt_x_f_v()
5947 void Riscv64Assembler::VFcvt_f_xu_v(VRegister vd, VRegister vs2, VM vm) {  in VFcvt_f_xu_v()  argument
5949   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFcvt_f_xu_v()
5950   const uint32_t funct7 = EncodeRVVF7(0b010010, vm);  in VFcvt_f_xu_v()
5954 void Riscv64Assembler::VFcvt_f_x_v(VRegister vd, VRegister vs2, VM vm) {  in VFcvt_f_x_v()  argument
5956   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFcvt_f_x_v()
5957   const uint32_t funct7 = EncodeRVVF7(0b010010, vm);  in VFcvt_f_x_v()
5961 void Riscv64Assembler::VFcvt_rtz_xu_f_v(VRegister vd, VRegister vs2, VM vm) {  in VFcvt_rtz_xu_f_v()  argument
5963   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFcvt_rtz_xu_f_v()
5964   const uint32_t funct7 = EncodeRVVF7(0b010010, vm);  in VFcvt_rtz_xu_f_v()
5968 void Riscv64Assembler::VFcvt_rtz_x_f_v(VRegister vd, VRegister vs2, VM vm) {  in VFcvt_rtz_x_f_v()  argument
5970   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFcvt_rtz_x_f_v()
5971   const uint32_t funct7 = EncodeRVVF7(0b010010, vm);  in VFcvt_rtz_x_f_v()
5975 void Riscv64Assembler::VFwcvt_xu_f_v(VRegister vd, VRegister vs2, VM vm) {  in VFwcvt_xu_f_v()  argument
5977   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFwcvt_xu_f_v()
5979   const uint32_t funct7 = EncodeRVVF7(0b010010, vm);  in VFwcvt_xu_f_v()
5983 void Riscv64Assembler::VFwcvt_x_f_v(VRegister vd, VRegister vs2, VM vm) {  in VFwcvt_x_f_v()  argument
5985   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFwcvt_x_f_v()
5987   const uint32_t funct7 = EncodeRVVF7(0b010010, vm);  in VFwcvt_x_f_v()
5991 void Riscv64Assembler::VFwcvt_f_xu_v(VRegister vd, VRegister vs2, VM vm) {  in VFwcvt_f_xu_v()  argument
5993   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFwcvt_f_xu_v()
5995   const uint32_t funct7 = EncodeRVVF7(0b010010, vm);  in VFwcvt_f_xu_v()
5999 void Riscv64Assembler::VFwcvt_f_x_v(VRegister vd, VRegister vs2, VM vm) {  in VFwcvt_f_x_v()  argument
6001   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFwcvt_f_x_v()
6003   const uint32_t funct7 = EncodeRVVF7(0b010010, vm);  in VFwcvt_f_x_v()
6007 void Riscv64Assembler::VFwcvt_f_f_v(VRegister vd, VRegister vs2, VM vm) {  in VFwcvt_f_f_v()  argument
6009   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFwcvt_f_f_v()
6011   const uint32_t funct7 = EncodeRVVF7(0b010010, vm);  in VFwcvt_f_f_v()
6015 void Riscv64Assembler::VFwcvt_rtz_xu_f_v(VRegister vd, VRegister vs2, VM vm) {  in VFwcvt_rtz_xu_f_v()  argument
6017   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFwcvt_rtz_xu_f_v()
6019   const uint32_t funct7 = EncodeRVVF7(0b010010, vm);  in VFwcvt_rtz_xu_f_v()
6023 void Riscv64Assembler::VFwcvt_rtz_x_f_v(VRegister vd, VRegister vs2, VM vm) {  in VFwcvt_rtz_x_f_v()  argument
6025   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFwcvt_rtz_x_f_v()
6027   const uint32_t funct7 = EncodeRVVF7(0b010010, vm);  in VFwcvt_rtz_x_f_v()
6031 void Riscv64Assembler::VFncvt_xu_f_w(VRegister vd, VRegister vs2, VM vm) {  in VFncvt_xu_f_w()  argument
6033   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFncvt_xu_f_w()
6034   const uint32_t funct7 = EncodeRVVF7(0b010010, vm);  in VFncvt_xu_f_w()
6038 void Riscv64Assembler::VFncvt_x_f_w(VRegister vd, VRegister vs2, VM vm) {  in VFncvt_x_f_w()  argument
6040   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFncvt_x_f_w()
6041   const uint32_t funct7 = EncodeRVVF7(0b010010, vm);  in VFncvt_x_f_w()
6045 void Riscv64Assembler::VFncvt_f_xu_w(VRegister vd, VRegister vs2, VM vm) {  in VFncvt_f_xu_w()  argument
6047   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFncvt_f_xu_w()
6048   const uint32_t funct7 = EncodeRVVF7(0b010010, vm);  in VFncvt_f_xu_w()
6052 void Riscv64Assembler::VFncvt_f_x_w(VRegister vd, VRegister vs2, VM vm) {  in VFncvt_f_x_w()  argument
6054   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFncvt_f_x_w()
6055   const uint32_t funct7 = EncodeRVVF7(0b010010, vm);  in VFncvt_f_x_w()
6059 void Riscv64Assembler::VFncvt_f_f_w(VRegister vd, VRegister vs2, VM vm) {  in VFncvt_f_f_w()  argument
6061   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFncvt_f_f_w()
6062   const uint32_t funct7 = EncodeRVVF7(0b010010, vm);  in VFncvt_f_f_w()
6066 void Riscv64Assembler::VFncvt_rod_f_f_w(VRegister vd, VRegister vs2, VM vm) {  in VFncvt_rod_f_f_w()  argument
6068   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFncvt_rod_f_f_w()
6069   const uint32_t funct7 = EncodeRVVF7(0b010010, vm);  in VFncvt_rod_f_f_w()
6073 void Riscv64Assembler::VFncvt_rtz_xu_f_w(VRegister vd, VRegister vs2, VM vm) {  in VFncvt_rtz_xu_f_w()  argument
6075   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFncvt_rtz_xu_f_w()
6076   const uint32_t funct7 = EncodeRVVF7(0b010010, vm);  in VFncvt_rtz_xu_f_w()
6080 void Riscv64Assembler::VFncvt_rtz_x_f_w(VRegister vd, VRegister vs2, VM vm) {  in VFncvt_rtz_x_f_w()  argument
6082   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFncvt_rtz_x_f_w()
6083   const uint32_t funct7 = EncodeRVVF7(0b010010, vm);  in VFncvt_rtz_x_f_w()
6087 void Riscv64Assembler::VFsqrt_v(VRegister vd, VRegister vs2, VM vm) {  in VFsqrt_v()  argument
6089   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFsqrt_v()
6090   const uint32_t funct7 = EncodeRVVF7(0b010011, vm);  in VFsqrt_v()
6094 void Riscv64Assembler::VFrsqrt7_v(VRegister vd, VRegister vs2, VM vm) {  in VFrsqrt7_v()  argument
6096   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFrsqrt7_v()
6097   const uint32_t funct7 = EncodeRVVF7(0b010011, vm);  in VFrsqrt7_v()
6101 void Riscv64Assembler::VFrec7_v(VRegister vd, VRegister vs2, VM vm) {  in VFrec7_v()  argument
6103   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFrec7_v()
6104   const uint32_t funct7 = EncodeRVVF7(0b010011, vm);  in VFrec7_v()
6108 void Riscv64Assembler::VFclass_v(VRegister vd, VRegister vs2, VM vm) {  in VFclass_v()  argument
6110   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VFclass_v()
6111   const uint32_t funct7 = EncodeRVVF7(0b010011, vm);  in VFclass_v()
6115 void Riscv64Assembler::VMsbf_m(VRegister vd, VRegister vs2, VM vm) {  in VMsbf_m()  argument
6117   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMsbf_m()
6119   const uint32_t funct7 = EncodeRVVF7(0b010100, vm);  in VMsbf_m()
6123 void Riscv64Assembler::VMsof_m(VRegister vd, VRegister vs2, VM vm) {  in VMsof_m()  argument
6125   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMsof_m()
6127   const uint32_t funct7 = EncodeRVVF7(0b010100, vm);  in VMsof_m()
6131 void Riscv64Assembler::VMsif_m(VRegister vd, VRegister vs2, VM vm) {  in VMsif_m()  argument
6133   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VMsif_m()
6135   const uint32_t funct7 = EncodeRVVF7(0b010100, vm);  in VMsif_m()
6139 void Riscv64Assembler::VIota_m(VRegister vd, VRegister vs2, VM vm) {  in VIota_m()  argument
6141   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VIota_m()
6143   const uint32_t funct7 = EncodeRVVF7(0b010100, vm);  in VIota_m()
6147 void Riscv64Assembler::VId_v(VRegister vd, VM vm) {  in VId_v()  argument
6149   DCHECK_IMPLIES(vm == VM::kV0_t, vd != V0);  in VId_v()
6150   const uint32_t funct7 = EncodeRVVF7(0b010100, vm);  in VId_v()