cache - OpenGrok history log for /XiangShan/src/test/scala/cache

Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
93447140	30-Oct-2019	Zihao Yu <[email protected]>	noop,Cache: wait for req.fire() when reading arrays * this solves the interference from coh /XiangShan/src/main/scala/noop/Cache.scala /XiangShan/src/main/scala/utils/SRAMTemplate.scala CacheTest.scala
af1c2328	30-Oct-2019	Zihao Yu <[email protected]>	test,CacheTest: add coherence input, test fails /XiangShan/src/main/scala/noop/Cache.scala CacheTest.scala
9a36b64c	26-Oct-2019	Zihao Yu <[email protected]>	test: add random cache test /XiangShan/.gitignore /XiangShan/Makefile /XiangShan/README.md /XiangShan/build.sbt /XiangShan/build.sc /XiangShan/debug/.gitignore /XiangShan/debug/Makefile /XiangShan/devlog.md /XiangShan/fpga/Makefile /XiangShan/fpga/Makefile.check /XiangShan/fpga/board/axu3cg/bd/prm.tcl /XiangShan/fpga/board/axu3cg/constr/hdmi.xdc /XiangShan/fpga/board/axu3cg/mk.tcl /XiangShan/fpga/board/axu3cg/rtl/addr_mapper.v /XiangShan/fpga/board/axu3cg/rtl/hdmi/i2c_config.v /XiangShan/fpga/board/axu3cg/rtl/hdmi/i2c_master_bit_ctrl.v /XiangShan/fpga/board/axu3cg/rtl/hdmi/i2c_master_byte_ctrl.v /XiangShan/fpga/board/axu3cg/rtl/hdmi/i2c_master_defines.v /XiangShan/fpga/board/axu3cg/rtl/hdmi/i2c_master_top.v /XiangShan/fpga/board/axu3cg/rtl/hdmi/timescale.v /XiangShan/fpga/board/axu3cg/rtl/system_top.v /XiangShan/fpga/board/common.tcl /XiangShan/fpga/board/ultraZ/bd/prm.tcl /XiangShan/fpga/board/ultraZ/constr/constr.xdc /XiangShan/fpga/board/ultraZ/mk.tcl /XiangShan/fpga/board/ultraZ/rtl/addr_mapper.v /XiangShan/fpga/board/ultraZ/rtl/system_top.v /XiangShan/fpga/board/zedboard/bd/prm.tcl /XiangShan/fpga/board/zedboard/constr/constr.xdc /XiangShan/fpga/board/zedboard/constr/vga.xdc /XiangShan/fpga/board/zedboard/mk.tcl /XiangShan/fpga/board/zedboard/rtl/addr_mapper.v /XiangShan/fpga/board/zedboard/rtl/system_top.v /XiangShan/fpga/boot/.gitignore /XiangShan/fpga/boot/README.md /XiangShan/fpga/boot/axu3cg/u-boot.elf /XiangShan/fpga/boot/bootgen-zynq.bif /XiangShan/fpga/boot/bootgen-zynqmp.bif /XiangShan/fpga/boot/bug-list.md /XiangShan/fpga/boot/mk.tcl /XiangShan/fpga/lib/include/axi.vh /XiangShan/fpga/noop.tcl /XiangShan/project/build.properties /XiangShan/scalastyle-config.xml /XiangShan/scalastyle-test-config.xml /XiangShan/scripts/vlsi_mem_gen /XiangShan/src/main/scala/bus/axi4/AXI4.scala /XiangShan/src/main/scala/bus/axi4/Delayer.scala /XiangShan/src/main/scala/bus/simplebus/Crossbar.scala /XiangShan/src/main/scala/bus/simplebus/DistributedMem.scala /XiangShan/src/main/scala/bus/simplebus/SimpleBus.scala /XiangShan/src/main/scala/bus/simplebus/ToAXI4.scala /XiangShan/src/main/scala/device/AXI4Keyboard.scala /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/device/AXI4Slave.scala /XiangShan/src/main/scala/device/AXI4Timer.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/device/AXI4VGA.scala /XiangShan/src/main/scala/gpu/GPU.scala /XiangShan/src/main/scala/noop/BPU.scala /XiangShan/src/main/scala/noop/Bundle.scala /XiangShan/src/main/scala/noop/Cache.scala /XiangShan/src/main/scala/noop/Decode.scala /XiangShan/src/main/scala/noop/EXU.scala /XiangShan/src/main/scala/noop/IDU.scala /XiangShan/src/main/scala/noop/IFU.scala /XiangShan/src/main/scala/noop/ISU.scala /XiangShan/src/main/scala/noop/NOOP.scala /XiangShan/src/main/scala/noop/NOOPTrap.scala /XiangShan/src/main/scala/noop/WBU.scala /XiangShan/src/main/scala/noop/fu/ALU.scala /XiangShan/src/main/scala/noop/fu/CSR.scala /XiangShan/src/main/scala/noop/fu/LSU.scala /XiangShan/src/main/scala/noop/fu/MDU.scala /XiangShan/src/main/scala/noop/fu/MOU.scala /XiangShan/src/main/scala/noop/isa/RVI.scala /XiangShan/src/main/scala/noop/isa/RVM.scala /XiangShan/src/main/scala/noop/isa/RVZicsr.scala /XiangShan/src/main/scala/noop/isa/RVZifencei.scala /XiangShan/src/main/scala/system/Coherence.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/TopMain.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/Debug.scala /XiangShan/src/main/scala/utils/FlushableQueue.scala /XiangShan/src/main/scala/utils/GTimer.scala /XiangShan/src/main/scala/utils/Hold.scala /XiangShan/src/main/scala/utils/LFSR64.scala /XiangShan/src/main/scala/utils/LatencyPipe.scala /XiangShan/src/main/scala/utils/LookupTree.scala /XiangShan/src/main/scala/utils/Pipeline.scala /XiangShan/src/main/scala/utils/RegMap.scala /XiangShan/src/main/scala/utils/SRAMTemplate.scala /XiangShan/src/main/scala/utils/StopWatch.scala /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/device.cpp /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/keyboard.cpp /XiangShan/src/test/csrc/macro.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/monitor.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/uart.cpp /XiangShan/src/test/csrc/vga.cpp CacheTest.scala /XiangShan/src/test/scala/top/NOOPSim.scala /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/vsrc/monitor.v /XiangShan/src/test/vsrc/ram.v /XiangShan/tools/readmemh/Makefile /XiangShan/tools/readmemh/gen-treadle-readmemh.c /XiangShan/tools/readmemh/groupby-4byte.c /XiangShan/tools/readmemh/split-readmemh.c
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