exu: vfadd.vf uopSplite

backend: update print info

VldIssue: backend support Vld issue

top-down: align top-down with Gem5 (#2085)

* topdown: add defines of topdown counters enum

* redirect: add redirect type for perf

* top-down: add stallReason IOs

frontend -> ctrlBlock -> de

top-down: align top-down with Gem5 (#2085)

* topdown: add defines of topdown counters enum

* redirect: add redirect type for perf

* top-down: add stallReason IOs

frontend -> ctrlBlock -> decode -> rename -> dispatch

* top-down: add dummy connections

* top-down: update TopdownCounters

* top-down: imp backend analysis and counter dump

* top-down: add HartId in `addSource`

* top-down: broadcast lqIdx of ROB head

* top-down: frontend signal done

* top-down: add memblock topdown interface

* Bump HuanCun: add TopDownMonitor

* top-down: receive and handle reasons in dispatch

* top-down: remove previous top-down code

* TopDown: add MemReqSource enum

* TopDown: extend mshr_latency range

* TopDown: add basic Req Source

TODO: distinguish prefetch

* dcache: distinguish L1DataPrefetch and CPUData

* top-down: comment out debugging perf counters in ibuffer

* TopDown: add path to pass MemReqSource to HuanCun

* TopDown: use simpler logic to count reqSource and update Probe count

* frontend: update topdown counters

* Update HuanCun Topdown for MemReqSource

* top-down: fix load stalls

* top-down: Change the priority of different stall reasons

* top-down: breakdown OtherCoreStall

* sbuffer: fix eviction

* when valid count reaches StoreBufferSize, do eviction

* sbuffer: fix replaceIdx

* If the way selected by the replacement algorithm cannot be written into dcache, its result is not used.

* dcache, ldu: fix vaddr in missqueue

This commit prevents the high bits of the virtual address from being truncated

* fix-ldst_pri-230506

* mainpipe: fix loadsAreComing

* top-down: disable dedup

* top-down: remove old top-down config

* top-down: split lq addr from ls_debug

* top-down: purge previous top-down code

* top-down: add debug_vaddr in LoadQueueReplay

* add source rob_head_other_repay

* remove load_l1_cache_stall_with/wihtou_bank_conflict

* dcache: split CPUData & refill latency

* split CPUData to CPUStoreData & CPULoadData & CPUAtomicData
* monitor refill latency for all type of req

* dcache: fix perfcounter in mq

* io.req.bits.cancel should be applied when counting req.fire

* TopDown: add TopDown for CPL2 in XiangShan

* top-down: add hartid params to L2Cache

* top-down: fix dispatch queue bound

* top-down: no DqStall when robFull

* topdown: buspmu support latency statistic (#2106)

* perf: add buspmu between L2 and L3, support name argument

* bump difftest

* perf: busmonitor supports latency stat

* config: fix cpl2 compatible problem

* bump utility

* bump coupledL2

* bump huancun

* misc: adapt to utility key&field

* config: fix key&field source, remove deprecated argument

* buspmu: remove debug print

* bump coupledl2&huancun

* top-down: fix sq full condition

* top-down: classify "lq full" load bound

* top-down: bump submodules

* bump coupledL2: fix reqSource in data path

* bump coupledL2

---------

Co-authored-by: tastynoob <[email protected]>
Co-authored-by: Guokai Chen <[email protected]>
Co-authored-by: lixin <[email protected]>
Co-authored-by: XiChen <[email protected]>
Co-authored-by: Zhou Yaoyang <[email protected]>
Co-authored-by: Lyn <[email protected]>
Co-authored-by: wakafa <[email protected]>

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backend: extend width of FuOpType

* use 9 bits FuOpType

Merge branch 'dev-vector' into new-backend

backend: refactor vset and add rab support

func(UopDivType): support vcompress & some insts of VIMac (#2067)

func(UopDivType): support UopDivType.VEC_COMPRESS & vcompress test pass
func(VIMac): add VIMac
pom(yunsuan): add VimacType

* fu

func(UopDivType): support vcompress & some insts of VIMac (#2067)

func(UopDivType): support UopDivType.VEC_COMPRESS & vcompress test pass
func(VIMac): add VIMac
pom(yunsuan): add VimacType

* func(UopDivType): support UopDivType.VEC_COMPRESS & vcompress test pass

* func(VIMac): add VIMac

1. support for vmul/vmvmulh/vmvmulhu/vmvmulhsu
2. support for vmacc/vnmsac/vmadd/vnmsub

* pom(yunsuan): add VimacType

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backend,vector: rewrite vset uop and base module

* Add unit-test for vset base module

add vset support

Co-authored-by: zhanglyGit <[email protected]>
Co-authored-by: Xuan Hu <[email protected]>

Decode: optimize coding style (#2063)

func(UopDivType): support VEC_RGATHER/VEC_RGATHER_VX/VEC_RGATHEREI16 of UopDivType

func(UopDivType): support VEC_VWW of UopDivType

Merge remote-tracking branch 'upstream/master' into new-backend

backend: merge v2backend into backend

backend,Core: remove dead code and comments

style(UopDivType): rename VEC_0MX/VEC_VMV/VEC_0MX_VFIRST to VEC_M0X/VEC_MVV/VEC_M0X_VFIRST

func(UopDivType): support VEC_0MX_VFIRST

func(UopDivType): support VEC_0MX/VEC_VMV/VEC_0MM

func(UopDivType): support VEC_SLIDEUP/VEC_ISLIDEUP/VEC_SLIDEDOWN/VEC_ISLIDEDOWN (#2028)

* func(UopDivType): support VEC_SLIDEUP/VEC_ISLIDEUP/VEC_SLIDEDOWN/VEC_ISLIDEDOWN

* pom(yunsuan): add isVsild

func(UopDivType): support VEC_SLIDEUP/VEC_ISLIDEUP/VEC_SLIDEDOWN/VEC_ISLIDEDOWN (#2028)

* func(UopDivType): support VEC_SLIDEUP/VEC_ISLIDEUP/VEC_SLIDEDOWN/VEC_ISLIDEDOWN

* pom(yunsuan): add isVsilde in VpermType & fix bugs of Permutation

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backend: refactor regfile rw parameters

* support float memory load/store
* refactor regfile read parameters
* replace `numSrc` with `numRegSrc` to notice the src data being from regfile
* refacto

backend: refactor regfile rw parameters

* support float memory load/store
* refactor regfile read parameters
* replace `numSrc` with `numRegSrc` to notice the src data being from regfile
* refactor BusyTable read port
* make int/vf BusyTable have the same number of read ports to simplify connection in Dispatch2Iq
* the unused read port will be optimized
* regular IQSize parameters
* split writeback port for scheduler into two kinds by reg types

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func(DecodeUnitComp): support VEC_VRED (#2017)

* func(DecodeUnitComp): support VEC_VRED of UopDivType

* fix(vxsat):fix bug that VPU's vxsat shout be arbitrated

* pom(yunsuan):fix Decode of vmvsx &

func(DecodeUnitComp): support VEC_VRED (#2017)

* func(DecodeUnitComp): support VEC_VRED of UopDivType

* fix(vxsat):fix bug that VPU's vxsat shout be arbitrated

* pom(yunsuan):fix Decode of vmvsx & add some test for VPERM

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func(DecodeUnitComp) : support vfslide1up & vslide1down & vfslide1down (#2012)

* func(DecodeUnitComp): support vfslide1up.vf

* func(DecodeUnitComp):support vslide1down & vfslide1down

* pom(yunsuan

func(DecodeUnitComp) : support vfslide1up & vslide1down & vfslide1down (#2012)

* func(DecodeUnitComp): support vfslide1up.vf

* func(DecodeUnitComp):support vslide1down & vfslide1down

* pom(yunsuan):add vfslide1up & vfslide1down

1. func(VFMA):add vfmsac, vfnmsac, vfmadd, vfnmadd, vfmsub, vfnmsub, vfwmul, vfwmacc, vfwnmacc, vfwmsac, vfwnmsac and their test supports
2. func(VpermType): add vfslide1up & vfslide1down

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pom(yunsuan): add IALU V3 (#2004)

1. func(VPERM): fix tail process, optimize vcompress, change vslide module name
2. func(VPERM): change to 2-stage
3. test(VPERM): add golden model and test: vslid

pom(yunsuan): add IALU V3 (#2004)

1. func(VPERM): fix tail process, optimize vcompress, change vslide module name
2. func(VPERM): change to 2-stage
3. test(VPERM): add golden model and test: vslidedown
4. test(VPERM): set vxsat=0 for vperm
5. test(VFADD): support vector-scalar operations func(VFADD): support vector-scalar operations
6. test: include
7. func(VFMA): add input:op_code,frs1,is_frs1; support vfmul.vv
8. func(VFMA):add vfmul.vf vfnmacc.vv vfnmacc.vf and their test supports
9. func(IALU):add IALU V3

* fix(decode): fix decode bug of selImm

1. fix decode bug of selImm
2. change VipuType to VpermType

* func(yunsuan): add VIAlu code v3

1. add VIAlu code v3
2. Update the IO of VFPU

* pom(yunsuan): add IALU V3

1. func(VPERM): fix tail process, optimize vcompress, change vslide module name
2. func(VPERM): change to 2-stage
3. test(VPERM): add golden model and test: vslidedown
4. test(VPERM): set vxsat=0 for vperm
5. test(VFADD): support vector-scalar operations func(VFADD): support vector-scalar operations
6. test: include <algorithm>
7. func(VFMA): add input:op_code,frs1,is_frs1; support vfmul.vv
8. func(VFMA):add vfmul.vf vfnmacc.vv vfnmacc.vf and their test supports
9. func(IALU):add IALU V3

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LoadMissTable: add it and use constant control (#1969)

* DCacheWrapper: add missdb and fix bug in `real_miss`

* DCacheWrapper: add constant control of missdb

* DCacheWrapper: correct the const

LoadMissTable: add it and use constant control (#1969)

* DCacheWrapper: add missdb and fix bug in `real_miss`

* DCacheWrapper: add constant control of missdb

* DCacheWrapper: correct the constant control logic

* databases: add constant control

* constantin: afix some bug

* constantin: fix txt

* fixbug: constant control in double core

* constantin: postfix changed in `verilator.mk`

* instDB: add robIdx and some TIME signals

* loadMissDB-copt: rm `resp.bits.firstHit` add `s2_first_hit`

* difftest: update

* yml: update the git workflow

* submodules: fix the binding commit-id of personal fork rep

* fix: github workflow add NOOP_HOME

because in constantin.scala use the absolute path of workdir by environment variable `NOOP_HOME`

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