NewCSR: set GVA=1 when hls insts trap load/store exceptions

NewCSR: refactor the encoding of CSROpType

Backend: add hypervisor exception definitions

Backend, RVH: fix coding conflicts between prefetch and hypervisor instruction (#3196)

rv64v: fix rfWen signal when writing x0 for vector instructions (#3107)

VLSU: Change the maximum number of 'numLsElem' dispatch by 'dispatch2iq'.

For emulation on Palladium, now the maximum 'numLsElem' number that can be emitted per port is:
16 2 2 2 2 2.

So vector i

VLSU: Change the maximum number of 'numLsElem' dispatch by 'dispatch2iq'.

For emulation on Palladium, now the maximum 'numLsElem' number that can be emitted per port is:
16 2 2 2 2 2.

So vector instructions other than 'unit-stride' can only be issued on the first port.
Scalars and 'unit-stride' instruction can be emitted at either port if the 'Lsq' allows allocation.

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package: change hypervior load's fuOpType (#3095)

This commit change `fuOpType` of `hlvxhu` and `hlvxwu` to avoid
conflicts with `vleff`. Besides, we also change `isHlv` and `isHlvx`.

Rename: v0 vl split

Decode: v0 vl split

FPU: fix f2v boxing error when higher bits are not all zeros (#3035)

FPU: fix f2v boxing error
set result as NAN when higher bit are not all zeros

Merge branch 'master' into vlsu-merge-master-0504

Rename: split fp and vec FreeList

riscv-zicond: Add Zicond Extension (#2941)

This PR added RISC-V Integer Conditional Operations Extension, which is
in the RVA23U64 Profile Mandatory Base. And the performance of
conditional move i

riscv-zicond: Add Zicond Extension (#2941)

This PR added RISC-V Integer Conditional Operations Extension, which is
in the RVA23U64 Profile Mandatory Base. And the performance of
conditional move instructions in micro-architecture is an interesting
point to explore.

Zicond instructions added: czero.eqz, czero.nez

Changes based on spec:

https://github.com/riscvarchive/riscv-zicond/releases/download/v1.0.1/riscv-zicond_1.0.1.pdf

Signed-off-by: Yangyu Chen <[email protected]>

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Merge branch 'master' into vlsu-tmp-master

Dispatch2Iq, package: make the encoding and decoding more standardized

Backend: support vector load&store better

* Todo: add more IQs for vector load&store
* Todo: make vector memory inst issue out of order
* Todo: fix bugs

rv64v: replace all i2f move instructions to i2v instructions

float: use VCVT module for all fcvt instructions
Co-authored-by: chengguanghui <[email protected]>

Merge remote-tracking branch 'upstream/master' into tmp-master

TODO: add gpaddr data path from frontend to backend

RVH: finish the desigh of H extention

rv64v: replace all i2f move instructions to i2v instructions

float: use VCVT module for all fcvt instructions
Co-authored-by: chengguanghui <[email protected]>

Backend: add vrorvi imm type

package: fix SelImm of Zvbb

Co-authored-by: Zhaoyang You <[email protected]>

Zvbb: support Zvbb instruction (#2686)

* support vandn,vbrev,vbrev8,vrev8,vclz,vctz,vcpop,vrol,vror,vwsll
* bump yunsuan: support Zvbb