misc: update PCL information (#899)

XiangShan is jointly released by ICT and PCL.

Add MulanPSL-2.0 License (#824)

In this commit, we add License for XiangShan project.

backend,RS: rewrite RS to optimize timing (#812)

* test,vcs: call $finish when difftest fails

* backend,RS: refactor with more submodules

This commit rewrites the reservation station in a more

backend,RS: rewrite RS to optimize timing (#812)

* test,vcs: call $finish when difftest fails

* backend,RS: refactor with more submodules

This commit rewrites the reservation station in a more configurable style.

The new RS has not finished.
- Support only integer instructions
- Feedback from load/store instructions is not supported
- Fast wakeup for multi-cycle instructions is not supported
- Submodules are refined later

* RS: use wakeup signals from arbiter.out

* RS: support feedback and re-schedule when needed

For load and store reservation stations, the instructions that left RS before may be
replayed later.

* test,vcs: check difftest_state and return on nemu trap instructions

* backend,RS: support floating-point operands and delayed regfile read for store RS

This commit adds support for floating-point instructions in reservation stations.
Beside, currently fp data for store operands come a cycle later than int data. This
feature is also supported.

Currently the RS should be ready for any circumstances.

* rs,status: don't trigger assertions when !status.valid

* test,vcs: add +workload option to specify the ram init file

* backend,rs: don't enqueue when redirect.valid or flush.valid

* backend,rs: support wait bit that instruction waits until store issues

This commit adds support for wait bit, which is mainly used in load and
store reservation stations to delay instruction issue until the corresponding
store instruction issued.

* backend,RS: optimize timing

This commit optimizes BypassNetwork and PayloadArray timing.

- duplicate bypass mask to avoid too many FO4
- use one-hot vec to get read data

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Backend: add mul to fast wakeup (#769)

* [WIP] Backend: add mul to fast wake-up

* Backend: handle mul wb priority and fix wrong delay

* RS: devide fastwakeup and nonBlocked(they were binded)

Perf: add perf counter to record rs wake up source (#792)

Refactor parameters, SimTop and difftest (#753)

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's

Refactor parameters, SimTop and difftest (#753)

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's manual, DPI-C calls should be more efficient than accessing from dut_ptr.
(2) DPI-C is cross-platform (Verilator, VCS, ...)
(3) difftest APIs are splited from emu.cpp to possibly support more backend platforms
(NEMU, Spike, ...)

The performance at this commit is quite slower than the original emu.
Performance issues will be fixed later.

* [WIP] SimTop: try to use 'XSTop' as soc

* CircularQueuePtr: ues F-bounded polymorphis instead implict helper

* Refactor parameters & Clean up code

* difftest: support basic difftest

* Support diffetst in new sim top

* Difftest; convert recode fmt to ieee754 when comparing fp regs

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Debug: add int/exc inst wb to debug queue

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Difftest: fix naive commit num limit

Co-authored-by: Yinan Xu <[email protected]>
Co-authored-by: William Wang <[email protected]>

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Merge remote-tracking branch 'origin/temp-mem-timing-merge' into mem-timing

PMA: fix pma check logic

Merge remote-tracking branch 'origin/master' into opt-exception

dispatch1: fix commitType

redirect: split conditional redirect and unconditional redirect

busyTable,srcState: change to 1bit

dispatch: optimize fuType usages

dispatch,MemBlock: optimize fuType usages

decode: change FuOpType to 6bits

Merge remote-tracking branch 'origin/master' into opt-queue-data

Merge pull request #437 from RISCVERS/dev-pma

PMA: add pma list

Auipc: get pc in jump unit

PMA: do pma check in tlb

PMA: use list instead of map for pma list

PMA: add PMA list

exceptionVec: use Vec(16, Bool()) for ExceptionVec()

roq: wrap writebackData in DataModuleTemplate

Merge remote-tracking branch 'origin/master' into opt-redirect

redirect: add redirect level to optimize redirect generation

roq: wrap data in RoqDataModule