func(vslide1up): support vslide1up instruction (#1990)

* func(decode+VIPU): support vslide1up instruction

* bump(yunsuan): func(VFADD) & VIPU type & test(VPERM)

refactor(VIPU): optimize decoding logic of VIPU

1. Some logic moves from VIPU.scala to VPUSubModule.scala
2. add VIAluFix

refactor(UopDivType): rename UopDivType & change VECTOR_TMP_REG_MV to FP_TMP_REG_MV

1. rename UopDivType
2. change VECTOR_TMP_REG_MV to FP_TMP_REG_MV
3. add UopDivType.VEC_MMM for decode of VMAND_MM

refactor(UopDivType): rename UopDivType & change VECTOR_TMP_REG_MV to FP_TMP_REG_MV

1. rename UopDivType
2. change VECTOR_TMP_REG_MV to FP_TMP_REG_MV
3. add UopDivType.VEC_MMM for decode of VMAND_MM VMANDN_MM ... VMXOR_MM

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decode: support mask instrutions UOP_DIV (#1975)

decode: support widening/narrowing/vsext/vzext instructions uop-div (#1963)

func(vxsat): add vxsat form VIPU to CSR

v2backend: huge tmp commit

support vmv.s.x and vx instruction(vadd.vx, vsub.vx) (#1951)

func(vmask): add vmask to the pipeline & support vmadc.vim

add DecodeUnitComp.scala and modify DecodeStage.scala for vector uop Div supporting(LMUL=8) (#1930)

* add DecodeUnitComp.scala and modify DecodeStage.scala for vector uop Div support(LMUL=8)

* ch

add DecodeUnitComp.scala and modify DecodeStage.scala for vector uop Div supporting(LMUL=8) (#1930)

* add DecodeUnitComp.scala and modify DecodeStage.scala for vector uop Div support(LMUL=8)

* changes made to implement a uop Div supporting with a cleaner code style(support Config)

* MaxNumOfUop parameterization supporting

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func(vfadd vfsub): support vfadd.vv vfsub.vv vfadd.vf vfsub.vf

TODO:ready-to-run need to update after 243c4e5ae53fe4(Ziyue-Zhang/NEMU_RVV/tree/master)

func(f2s vslide1up): support VppuType.f2s & VppuType.vslide1up

1. style(isVpu): delete isVpu in FuType
2. support VppuType.f2s & VppuType.vslide1up & generate verilog sucessful

rs: assert when 'valid' & (wrong srcType || multi-waked up)

v2backend: complete dummy params of backend

fix(package): fix bug of SelImm.IMM_S and SelImm.X code conflicts

v2backend: use OH FuType

backend,vector: fix vector relative bug and first vadd instr success

Modification and Bugs includes:
1. readFpRf/writeFpRf is replaced with readFpVecRf/writeFpVecRf in some
places;
2. fpWen is repla

backend,vector: fix vector relative bug and first vadd instr success

Modification and Bugs includes:
1. readFpRf/writeFpRf is replaced with readFpVecRf/writeFpVecRf in some
places;
2. fpWen is replaced with fpVecWen in some places;
3. add ADD/SUB decode info
4. dispatch logic modification
5. dataWidth & wakeup logic in rs
6. ExuInput/ExuOutput at many places
7. fuSel inside FUBlock of FMAC
8. FuType encoding
9. many other bugs

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Backend: add new version bundles

vset: add vset instr support

Decoder: refactor and replace rocketchip.decoder with ListLookUp

* Use default params to avoid modification when adding new decode fields
* Add new decode field "vecWen"
* Replace rocketchip.decoder

Decoder: refactor and replace rocketchip.decoder with ListLookUp

* Use default params to avoid modification when adding new decode fields
* Add new decode field "vecWen"
* Replace rocketchip.decoder with ListLookUp
* chisel3.minimizer causes Java OutOfMemory exception or function params error when adding new vector insts
* Replace all X's with 0's, since the type param of ListLookUp must inherit chisel3.Data and BitPat does not inherit from chisel3.Data

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dispatch: let vec uops use fp and mem ports

Decoder: add decoder table for vset and vls

Decoder: add vecDecoder for OPIVV, OPIVX, OPIVI

Co-authored-by: fdy <[email protected]>

bump yunsuan, mv V[if]puType into yunsuan

vpu: add vipu(with adder that not works) into fmacExeUnit