StoreQueue: fix X when write StoreBuffer (#3068)

If there is an inactive element in a vector access instruction, it will
not be sent to the sta pipeline, so the data in the corresponding entry
in

StoreQueue: fix X when write StoreBuffer (#3068)

If there is an inactive element in a vector access instruction, it will
not be sent to the sta pipeline, so the data in the corresponding entry
in the StoreQueue is invalid, and we use `vecValid` to differentiate
between valid and invalid data in table entries.

For StoreQueue entries, `vecValid` depends on `hasException`,
`vecDataValid` (whether the data in the table entry is valid or not),
and `isVec` (whether it is a table entry for a vector instruction or
not). `vecDataValid` is initialized to false, and will be set to true
when sta writes back to the entry and the entry is a vector instruction.

Only vector instructions have invalid data in table entries, because we
can't determine how many table entries are needed for a vector access
uop at dispatch time.

show more ...

VirtualLoadQueue: remove useless logic (#3066)

Revert "LSQ: optimize static clock gating coverage (#3023)" (#3055)

LSQ: refactor vector load/store commit judging logic to fix X in vcs (#3048)

LSQ: use RegNextWithEnable when RegEnable.next contains RegEnable.enable (#3046)

StoreQueue: fix bug after refactor commit logic (#3041)

CoupledL2, Uncache, LSQ: support non-data error handling (#3042)

According to CHI specification, a non-data error should be reported when
an error is detected that is not related to data corruption

CoupledL2, Uncache, LSQ: support non-data error handling (#3042)

According to CHI specification, a non-data error should be reported when
an error is detected that is not related to data corruption. Typically
this error is reported for:
* An attempt to access a location that does not exist.
* An illegal access, such as a write to a read only location.
* An attempt to use a transaction type that is not supported.

While the second kind of errors can be resolved by PMA, the first and
the third kind of errors were not supported yet.

This commit implements non-data error handling path. MMIOBridge in
CoupledL2 transfers CHI `RespErr` field downwards into TileLink `denied`
field upwards. Uncache in DCache passes the error to LSQ to generate
access fault exception:
* For MMIO loads, UncacheBuffer writes back `exceptionVec` to LoadUnit
s0 and informs exception address to ExceptionBuffer at the same time.
* For MMIO stores, SQ writes back `exceptionVec` to Backend directly.

BTW, data error is still not supported.

show more ...

clockgate: set default initialization with 0 to fix X in vcs (#3031)

StoreQueue: Commit storequeue entry by judging robidx (#3020)

In the previous design, for scalar store commands, commits were made
based on the `scommit` passed in by rob. That is, after rob commit

StoreQueue: Commit storequeue entry by judging robidx (#3020)

In the previous design, for scalar store commands, commits were made
based on the `scommit` passed in by rob. That is, after rob commits n
store commands in one cycle, it sets scommit to n, and the storequeue
needs to commit n entries based on the value of scommit.

Due to the special nature of vector instructions, a vector store
instruction may correspond to a maximum of 128 items, and it is not
possible to use `scommit` commits, which are similar to scalar commits.

In this modification, both vector and scalar directives are compared
against `robidx`, and the storequeue entry is committed when the `uop`
stored in `uop` is equal to or older than the `pendingptr` passed in by
rob. This has some improvement on timing.

Also, additional processing is currently required for vector
instructions. When an exception occurs on an item, it needs to be
handled with an out-of-queue, but not write sbuffer.

show more ...

LSQ: optimize static clock gating coverage (#3023)

LoadqueueReplay: Entry should be allocated when matching mergebuffer feedback (#3010)

StoreQueue: fix the bug of addrReadyVec.

This commit fix the situation that inactive element will not send to pipeline, which cause stAddrReadyVec always false.

StoreQueue: fix the assigment condition of 'vecCommit'

'vecCommit' also needs to determine if it has been allocated

StoreQueue: re-enter exceptionbuffer when store_s2

storeunit will resp some exception (misaligned or pagefault) when store_s1,
however, pmp will raise access fault when store_s2, which should be wri

StoreQueue: re-enter exceptionbuffer when store_s2

storeunit will resp some exception (misaligned or pagefault) when store_s1,
however, pmp will raise access fault when store_s2, which should be written into exceptionbuffer

show more ...

StoreQueue: fix vector store commit

this commit delay vector commit flag 1 cycle, because of scala store commit flag need delay 1 cycle. Ensure that there will be no situation where subsequent vecto

StoreQueue: fix vector store commit

this commit delay vector commit flag 1 cycle, because of scala store commit flag need delay 1 cycle. Ensure that there will be no situation where subsequent vector store are submitted and the previous scala store is not submitted.

show more ...

StoreQueue: fix port uninitialized when difftest was unenabled

VLSU: fix faulty exception vaddr selection logic

Merge branch 'master' into vlsu-merge-master-0504

IFU & GPAMem, RVH: fix the bug about getting gpa (#2960)

1. Delete some useless codes about gpaddr.
2. fix the bugs about wrong gpa was writen in mtval2 or htval when guest
page fault occured

Bump utility and disable ConstantIn by default (#2955)

* use BigInt for initValue of Constantin.createRecord
* use WITH_CONSTANTIN=1 to enable the ConstantIn plugin

VLSU: fix vector exception vaddr calculation

This commit fix the bug of vector exception vaddr calculation, need to send exceptionVec to exceptionBuffer.

Merge branch 'master' into vlsu-tmp-master

VLSU, lsq: support more than one vector pipeline

VLSU, StoreQueue: fix bug of vector store out-of-order commit

Memblock, LoadReplayQueue: fix bug of ageMatrix enq && deq

LoadReplayQueue: fix age matrix dequeue