ifu: add ftqEnqbuf log

ftq and all: now we can compile

DecodeUnit/IFU: move RVC expander to frontend if4

fix refill when flush bug

For single port SRAM icache, we disable read when write. So we disable
if1_cango when flush if2 register

[WIP] connect Ftq into ctrl block

Perf: Modify perdictors counter calc logic

Perf: Add counter for predictors

Merge branch 'master' into icache-uncache

icache: add not bus-width aligned MMIO req support

IFU: add mmio aligned function

IFU: set reset vector to 0x10000000

ICache-uncache add MMIO perf register

IFU: add MMIO parameters

Perf: Fix a bug and it still wrong

icache: add icache uncache support

Perf: Modify predictor counter logic

Perf: Add BPU pred pref counter

Merge branch 'master' into opt-ibuf

ifu: don't use if4_pc to check if4_prevHalfInstrMet

bpu: remove flush signals

IFU: fix instruction block bug

if1_can_go depend on itlb_resp_valid but not considering !if2_valid

Merge branch 'ifu-pakcet-aligned' of https://github.com/RISCVERS/XiangShan into ifu-pakcet-aligned

ifu: fix jal target calculation bug

IFU: tlb_resp_valid processing in advance

The path for TLB to generate miss signal is too long, so we
decoupled the tlb_resp_valid signal from if2_ready and
icache_req_ready. It is now c

IFU: tlb_resp_valid processing in advance

The path for TLB to generate miss signal is too long, so we
decoupled the tlb_resp_valid signal from if2_ready and
icache_req_ready. It is now connected to if1_fire with a AND logic
to generate if1_can_go. The if1_can_go signal is sent to BPU and Icache as the
signal that say the first stage can be passed down.

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Frontend/IFU: place L1plusPrefetcher in Frontend

ifu: code clean ups

ifu, bpu: totally remove the concept of 'bank'