fix(PTW, RVH): modify the logic of checking high bits of gpaddr (#3679)

- In PTW, use a reg to store gvpn to check the high bits.
- The len of gvpn(wire type) is wrong. It should be ptePPNLen.

fix(PTW, RVH): add the high bits check of the first s2xlate when the req is allstage (#3681)

fix(pbmt): fix assignment bug in tlb (#3770)

fix(TLB): Should not send gpa when prefetch or redirect (#3697)

In our previous design, it was assumed that a request for gpaddr would
always be replayed until it was responsed. However, this condi

fix(TLB): Should not send gpa when prefetch or redirect (#3697)

In our previous design, it was assumed that a request for gpaddr would
always be replayed until it was responsed. However, this condition is
not satisfied for prefetch and redirected requests, resulting in stuck.
This commit fixes this bug.

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fix(TLB, RVH): delete the s1tagfix which maybe cause the tag check to fail (#3685)

fix(tlb): overwrite resp information when high address exception happens (#3674)

fix(PTW, RVH): fix the priority of gpf, gaf and gvpn_gpf in PTW (#3657)

If hptw resp gpf or gaf, the gvpn_gpf should not be valid. The pr fixes
the bug that gvpn_gpf is valid after hptw resp gpf or

fix(PTW, RVH): fix the priority of gpf, gaf and gvpn_gpf in PTW (#3657)

If hptw resp gpf or gaf, the gvpn_gpf should not be valid. The pr fixes
the bug that gvpn_gpf is valid after hptw resp gpf or gaf.

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fix(PTW, RVH): add the check A bit in HPTW when G-stage is for VS-stage (#3660)

fix(exception): fix exception vaddr generate logic (#3639)

In LSU, for exceptions that can be detected before address
translation(`preaf`, `prepf` or `pregpf`), the original vaddr should be
retain

fix(exception): fix exception vaddr generate logic (#3639)

In LSU, for exceptions that can be detected before address
translation(`preaf`, `prepf` or `pregpf`), the original vaddr should be
retained. And for exceptions detected after address translation, the
48-bit vaddr needs to be zero-extended or sign-extended according to
different modes(`GenExceptionVa`), and then write to *tval.

Also fix some connection bugs.

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fix(Pmem): memory range should be 'or'ed rather than 'and'ed (#3651)

fix(TLB): fix exception judgement condition (#3629)

A TLB query requires two cycles, the first (s0) to receive the req and
the second (s1) to return the result. pre exception checking will be
done

fix(TLB): fix exception judgement condition (#3629)

A TLB query requires two cycles, the first (s0) to receive the req and
the second (s1) to return the result. pre exception checking will be
done on the first cycle, so should use `vmenable` and `s2xlateEnable` of
the first cycle.

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refactor(HPM): move HPMs from utils to utility repo (#3631)

Because HPMs will be used in Coupled L2 as well, delete
`PerfCounterUtils.scala` in Xiangshan and create
`HardwarePerfMonitor.scala` in

refactor(HPM): move HPMs from utils to utility repo (#3631)

Because HPMs will be used in Coupled L2 as well, delete
`PerfCounterUtils.scala` in Xiangshan and create
`HardwarePerfMonitor.scala` in Utility.
See also [Pull Request in
CoupledL2](https://github.com/OpenXiangShan/CoupledL2/pull/251#discussion_r1770738535).

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fix(PTW, RVH): fix the gpa high check fail in last s2xlate due to a change of gpaddr (#3624)

fix(PageTableCache): fix hit & bypass logic when onlypf (#3625)

fix(TLB): Should check vmid when s2xlate in wbhit (#3623)

feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault t

feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault traps that meet
both of the following conditions:
- the trap is caused by a G-stage translation which supports VS-stage
translation
- a nonzero value is written to mtval2/htval

"isForVSnonLeafPTE" is used only in exceptional circumstances that gpf
happens in the G-stage translation which supports VS-stage translation,
such as searching the non-leaf pte of VS-stage.

This patch adds support for writing proper value to mtinst/htinst when
specific trap occurs. And bump the nemu.

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refactor(Pmem): use `Seq` for physical memory ranges (#3622)

fix(PageTableWalker): last_s2xlate should be false when exception occurs (#3614)

fix(prefetch): MMIO address should not send prefetch requests (#3615)

TODO: Prefetcher should check pmp & pma in order to decide whether to
send requests

fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exc

fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exceptions in such cases.

Commit
https://github.com/OpenXiangShan/XiangShan/commit/c1b28b66879239a5b3a44741376f3b002e8ac834
has already fixed high address bits checking of jump target. This commit
fixes lsu part, checking full address in tlb and passing full address
directly to csr.

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chore(MMU): Remove timeout assertion (#3603)

With CHI enabled and CMN connected, a transaction may last over
timeoutThreshold. So this commit removes it (also since L2 Cache will
detect timeout)

fix(PageTableCache): fix ptwcache refill logic when exception (#3588)

Since L2 Cache access width is 512 bits, 8 PTE items are refilled into
page cache together. In previous design, when an excepti

fix(PageTableCache): fix ptwcache refill logic when exception (#3588)

Since L2 Cache access width is 512 bits, 8 PTE items are refilled into
page cache together. In previous design, when an exception occurs in one
of the 8 refilled PTE entries, none of the 8 entries will be refilled.
In this case, if there is a normal entry in one of the 8 neighbouring
page tables, it will not be refillled because of the exception in the
other entries, which will lead to blocking.

This commit fixes this problem. `vs` means that if one of the 8
consecutive page tables has an exception, the corresponding `vs` will be
forced to be false when judging hit. `onlypf` means that if x2slate is
not enabled, and only pf occurs, then the pf information will be
returned. Except for the onlypf case, the rest of the exceptions will
not be refilled in page cache (none of them will hit).

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fix(TLB, RVH): fix the bug that pf happens because s1 is nonleaf (#3580)

fix(PTW, RVH): fix the wrong state transition when has gpf or gaf (#3575)

fix(L1TLB, RVH): fix the wrong pf because the perm check of fake pte (#3553)