rename - OpenGrok history log for /XiangShan/src/main/scala/xiangshan/backend/rename

Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
621007d9	12-Mar-2023	Xuan Hu <[email protected]>	backend: remove soft prefetch hint insts temporary Todo: revert this when mem block connected /XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala Rename.scala /XiangShan/src/main/scala/xiangshan/v2backend/fu/DivUnit.scala
3d1a5c10	11-Mar-2023	maliao <[email protected]>	Rob: Add Rab module to support separate commit of uops and instructions (#1956) /XiangShan/difftest /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FUBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VFPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationBase.scala Rename.scala RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/yunsuan
4e5d06f1	08-Mar-2023	zhanglyGit <[email protected]>	decode: modify vx instruction uops and fix bug (#1952) /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala Rename.scala RenameTable.scala freelist/StdFreeList.scala
3b739f49	06-Mar-2023	Xuan Hu <[email protected]>	v2backend: huge tmp commit /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FUBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/ctrlblock/MemCtrl.scala /XiangShan/src/main/scala/xiangshan/backend/ctrlblock/RedirectGenerator.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Rs.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Bku.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Branch.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Vsetu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/PayloadArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationALU.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationBase.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationFMA.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationFMisc.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationJump.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationLoad.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationMisc.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationMul.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationSta.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationStd.scala /XiangShan/src/main/scala/xiangshan/backend/issue/SelectPolicy.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/MemVectorInterface.scala /XiangShan/src/main/scala/xiangshan/newBackend/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/newBackend/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/newBackend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xiangshan/v2backend/Backend.scala /XiangShan/src/main/scala/xiangshan/v2backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/v2backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/v2backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/v2backend/DataPath.scala /XiangShan/src/main/scala/xiangshan/v2backend/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/v2backend/IssueBlock.scala /XiangShan/src/main/scala/xiangshan/v2backend/RegFile.scala /XiangShan/src/main/scala/xiangshan/v2backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/v2backend/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/v2backend/ctrlblock/MemCtrl.scala /XiangShan/src/main/scala/xiangshan/v2backend/ctrlblock/RedirectGen.scala /XiangShan/src/main/scala/xiangshan/v2backend/dispatch/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/v2backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/v2backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/v2backend/fu/BranchUnit.scala /XiangShan/src/main/scala/xiangshan/v2backend/fu/DivUnit.scala /XiangShan/src/main/scala/xiangshan/v2backend/fu/FuncUnit.scala /XiangShan/src/main/scala/xiangshan/v2backend/fu/JumpUnit.scala /XiangShan/src/main/scala/xiangshan/v2backend/fu/MulUnit.scala /XiangShan/src/main/scala/xiangshan/v2backend/issue/DeqPolicy.scala /XiangShan/src/main/scala/xiangshan/v2backend/issue/EnqPolicy.scala /XiangShan/src/main/scala/xiangshan/v2backend/issue/ImmExtractor.scala /XiangShan/src/main/scala/xiangshan/v2backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/v2backend/issue/StatusArray.scala /XiangShan/src/main/scala/xiangshan/v2backend/package.scala /XiangShan/src/test/scala/xiangshan/v2backend/BackendMain.scala /XiangShan/src/test/scala/xiangshan/v2backend/DataPathMain.scala /XiangShan/src/test/scala/xiangshan/v2backend/SchedulerMain.scala /XiangShan/src/test/scala/xiangshan/v2backend/dispatch/Dispatch2IqMain.scala /XiangShan/src/test/scala/xiangshan/v2backend/issue/DataArrayMain.scala /XiangShan/src/test/scala/xiangshan/v2backend/issue/IssueQueueMain.scala /XiangShan/src/test/scala/xiangshan/v2backend/issue/StatusArrayMain.scala
22d6635a	06-Mar-2023	zhanglyGit <[email protected]>	support vmv.s.x and vx instruction(vadd.vx, vsub.vx) (#1951) /XiangShan/Makefile /XiangShan/Makefile.test /XiangShan/build.sc /XiangShan/debug/local_ci.py /XiangShan/difftest /XiangShan/ready-to-run /XiangShan/scripts/constantHelper.py /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/utils/OverrideableQueue.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Branch.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Vsetu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VFPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VPPU.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationBase.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala Rename.scala RenameTable.scala freelist/StdFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/RefillPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/AsynchronousMetaArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/MemTrace.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchInterface.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/fu/IntDiv.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/src/test/scala/xiangshan/DecodeTest.scala /XiangShan/src/test/scala/xiangshan/XSTester.scala /XiangShan/utility /XiangShan/yunsuan
925ac328	08-Feb-2023	xiwenx <[email protected]>	vset: pass lsrc0NotZero by imm(15) & modify vl calculation logic in alu (#1903) 1. pass lsrc0NotZero by imm(15) 2. modify the logic for generating vl in Alu /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Branch.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala Rename.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xiangshan/v2backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/v2backend/BackendTop.scala /XiangShan/src/main/scala/xiangshan/v2backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/v2backend/DataPath.scala /XiangShan/src/main/scala/xiangshan/v2backend/RegFile.scala /XiangShan/src/main/scala/xiangshan/v2backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/v2backend/dispatch/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/v2backend/issue/DataArray.scala /XiangShan/src/main/scala/xiangshan/v2backend/issue/DeqPolicy.scala /XiangShan/src/main/scala/xiangshan/v2backend/issue/EnqPolicy.scala /XiangShan/src/main/scala/xiangshan/v2backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/v2backend/issue/StatusArray.scala /XiangShan/src/main/scala/xiangshan/v2backend/package.scala /XiangShan/src/test/scala/xiangshan/v2backend/DataPathMain.scala /XiangShan/src/test/scala/xiangshan/v2backend/SchedulerMain.scala /XiangShan/src/test/scala/xiangshan/v2backend/dispatch/Dispatch2IqMain.scala /XiangShan/src/test/scala/xiangshan/v2backend/issue/DataArrayMain.scala /XiangShan/src/test/scala/xiangshan/v2backend/issue/IssueQueueMain.scala /XiangShan/src/test/scala/xiangshan/v2backend/issue/StatusArrayMain.scala
c515baa2	08-Feb-2023	xiwenx <[email protected]>	vset: pass lsrc0NotZero by imm(15) & modify vl calculation logic in alu (#1903) 1. pass lsrc0NotZero by imm(15) 2. modify the logic for generating vl in Alu /XiangShan/difftest /XiangShan/huancun /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Branch.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/package.scala
0f038924	16-Jan-2023	ZhangZifei <[email protected]>	backend,vector: fix vector relative bug and first vadd instr success Modification and Bugs includes: 1. readFpRf/writeFpRf is replaced with readFpVecRf/writeFpVecRf in some places; 2. fpWen is repla backend,vector: fix vector relative bug and first vadd instr success Modification and Bugs includes: 1. readFpRf/writeFpRf is replaced with readFpVecRf/writeFpVecRf in some places; 2. fpWen is replaced with fpVecWen in some places; 3. add ADD/SUB decode info 4. dispatch logic modification 5. dataWidth & wakeup logic in rs 6. ExuInput/ExuOutput at many places 7. fuSel inside FUBlock of FMAC 8. FuType encoding 9. many other bugs show more ... /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/FUBlock.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Rs.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationBase.scala /XiangShan/src/main/scala/xiangshan/backend/issue/WakeupQueue.scala Rename.scala freelist/StdFreeList.scala /XiangShan/src/main/scala/xiangshan/package.scala
4aa9ed34	12-Jan-2023	fdy <[email protected]>	vset: add vset instr support /XiangShan/.gitignore /XiangShan/Makefile /XiangShan/build.sc /XiangShan/difftest /XiangShan/ready-to-run /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FUBlock.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationALU.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationBase.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationFMA.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationFMisc.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationJump.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationLoad.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationMul.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationSta.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationStd.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala Rename.scala freelist/MEFreeList.scala freelist/RefCounter.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWPU.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/yunsuan
0ef1b3c2	03-Jan-2023	ZhangZifei <[email protected]>	Merge remote-tracking branch 'origin/master' into rf-after-issue /XiangShan/.github/workflows/check_verilog.py /XiangShan/difftest /XiangShan/fudian /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/device/RocketDebugWrapper.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationBase.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationMisc.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala freelist/MEFreeList.scala freelist/RefCounter.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/AsynchronousMetaArray.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/utility
67ba96b4	02-Jan-2023	Yinan Xu <[email protected]>	Switch to asynchronous reset for all modules (#1867) This commit changes the reset of all modules to asynchronous style, including changes on the initialization values of some registers. For async Switch to asynchronous reset for all modules (#1867) This commit changes the reset of all modules to asynchronous style, including changes on the initialization values of some registers. For async registers, they must have constant reset values. show more ... /XiangShan/.github/workflows/check_verilog.py /XiangShan/difftest /XiangShan/fudian /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/device/RocketDebugWrapper.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala freelist/MEFreeList.scala freelist/RefCounter.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/AsynchronousMetaArray.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/utility
b6c99e8e	29-Dec-2022	ZhangZifei <[email protected]>	Merge remote-tracking branch 'origin/master' into rf-after-issue /XiangShan/.gitmodules /XiangShan/build.sc /XiangShan/difftest /XiangShan/huancun /XiangShan/ready-to-run /XiangShan/src/main/scala/device/AXI4DummySD.scala /XiangShan/src/main/scala/device/AXI4Flash.scala /XiangShan/src/main/scala/device/AXI4IntrGenerator.scala /XiangShan/src/main/scala/device/AXI4Keyboard.scala /XiangShan/src/main/scala/device/AXI4Memory.scala /XiangShan/src/main/scala/device/AXI4Plic.scala /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/device/AXI4SlaveModule.scala /XiangShan/src/main/scala/device/AXI4Timer.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/device/AXI4VGA.scala /XiangShan/src/main/scala/device/TLPMA/TLPMA.scala /XiangShan/src/main/scala/gpu/GPU.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FUBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Rs.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/IndexMapping.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Bku.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/InputBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Radix2Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala /XiangShan/src/main/scala/xiangshan/backend/issue/BypassNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/PayloadArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationBase.scala /XiangShan/src/main/scala/xiangshan/backend/issue/SelectPolicy.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/WakeupQueue.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala BusyTable.scala Rename.scala RenameTable.scala freelist/BaseFreeList.scala freelist/MEFreeList.scala freelist/RefCounter.scala freelist/StdFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/CacheInstruction.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/FakeDCache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/AbstractDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/MetaArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLBMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TlbPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/BestOffsetPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/Prefetcher.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/StreamPrefetch.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Composer.scala /XiangShan/src/main/scala/xiangshan/frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/frontend/FauFTB.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/WrBypass.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/InstrUncache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ReleaseUnit.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ReplacePipe.scala /XiangShan/src/main/scala/xiangshan/mem/MaskedDataModule.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/WaitTable.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/DatamoduleResultBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/DummyVLSQ.scala /XiangShan/src/main/scala/xiangshan/mem/vector/MemVectorInterface.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/utility
40a70bd6	25-Dec-2022	ZhangZifei <[email protected]>	backend: change vector relative IO to 128bits /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FUBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala RenameTable.scala
3c02ee8f	25-Dec-2022	wakafa <[email protected]>	Separate Utility submodule from XiangShan (#1861) * misc: add utility submodule * misc: adjust to new utility framework * bump utility: revert resetgen * bump huancun /XiangShan/.gitmodules /XiangShan/build.sc /XiangShan/difftest /XiangShan/huancun /XiangShan/ready-to-run /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/device/AXI4DummySD.scala /XiangShan/src/main/scala/device/AXI4Flash.scala /XiangShan/src/main/scala/device/AXI4IntrGenerator.scala /XiangShan/src/main/scala/device/AXI4Keyboard.scala /XiangShan/src/main/scala/device/AXI4Memory.scala /XiangShan/src/main/scala/device/AXI4Plic.scala /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/device/AXI4SlaveModule.scala /XiangShan/src/main/scala/device/AXI4Timer.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/device/AXI4VGA.scala /XiangShan/src/main/scala/device/TLPMA/TLPMA.scala /XiangShan/src/main/scala/gpu/GPU.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FUBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Rs.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/IndexMapping.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Bku.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/InputBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Radix2Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala /XiangShan/src/main/scala/xiangshan/backend/issue/BypassNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/PayloadArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/issue/SelectPolicy.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/WakeupQueue.scala BusyTable.scala Rename.scala RenameTable.scala freelist/BaseFreeList.scala freelist/MEFreeList.scala freelist/RefCounter.scala freelist/StdFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/CacheInstruction.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/FakeDCache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/AbstractDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/RefillPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/AsynchronousMetaArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/MetaArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLBMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TlbPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/BestOffsetPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/Prefetcher.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/StreamPrefetch.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Composer.scala /XiangShan/src/main/scala/xiangshan/frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/frontend/FauFTB.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/WrBypass.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/InstrUncache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ReleaseUnit.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ReplacePipe.scala /XiangShan/src/main/scala/xiangshan/mem/MaskedDataModule.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/WaitTable.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/DatamoduleResultBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/DummyVLSQ.scala /XiangShan/src/main/scala/xiangshan/mem/vector/MemVectorInterface.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/utility
4bc8d977	25-Dec-2022	ZhangZifei <[email protected]>	rename: fix bug of freelist number cause by mixed v/f reg /XiangShan/.gitmodules /XiangShan/build.sc /XiangShan/difftest /XiangShan/ready-to-run /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala Rename.scala freelist/StdFreeList.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/yunsuan
a7a8a6cc	15-Dec-2022	Haojin Tang <[email protected]>	rename: use intRat for vconfig; add a vec read port /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala Rename.scala RenameTable.scala
deb6421e	14-Dec-2022	Haojin Tang <[email protected]>	vector rename: support vector register rename /XiangShan/difftest /XiangShan/ready-to-run /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/utils/DataModuleTemplate.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FUBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala /XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationALU.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationBase.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationFMA.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationFMisc.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationJump.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationLoad.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationMisc.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationMul.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationSta.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationStd.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala Rename.scala RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/CacheInstruction.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/RefillPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/AsynchronousMetaArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TlbPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/mem/MaskedDataModule.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/DummyVLSQ.scala /XiangShan/src/main/scala/xiangshan/mem/vector/MemVectorInterface.scala /XiangShan/src/main/scala/xiangshan/package.scala
eb163ef0	17-Nov-2022	Haojin Tang <[email protected]>	top-down: introduce top-down counters and scripts (#1803) * top-down: add initial top-down features * rob600: enlarge queue/buffer size * :art: After git pull * :sparkles: Add BranchResteer top-down: introduce top-down counters and scripts (#1803) * top-down: add initial top-down features * rob600: enlarge queue/buffer size * :art: After git pull * :sparkles: Add BranchResteers->CtrlBlock * :sparkles: Cg BranchResteers after pending * :sparkles: Add robflush_bubble & ldReplay_bubble * :ambulance: Fix loadReplay->loadReplay.valid * :art: Dlt printf * :sparkles: Add stage2_redirect_cycles->CtrlBlock * :saprkles: CtrlBlock:Add s2Redirect_when_pending * :sparkles: ID:Add ifu2id_allNO_cycle * :sparkles: Add ifu2ibuffer_validCnt * :sparkles: Add ibuffer_IDWidth_hvButNotFull * :sparkles: Fix ifu2ibuffer_validCnt * :ambulance: Fix ibuffer_IDWidth_hvButNotFull * :sparkles: Fix ifu2ibuffer_validCnt->stop * feat(buggy): parameterize load/store pipeline, etc. * fix: use LoadPipelineWidth rather than LoadQueueSize * fix: parameterize `rdataPtrExtNext` * fix(SBuffer): fix idx update logic * fix(Sbuffer): use `&&` to generate flushMask instead of `\|\|` * fix(atomic): parameterize atomic logic in `MemBlock` * fix(StoreQueue): update allow enque requirement * chore: update comments, requirements and assertions * chore: refactor some Mux to meet original logic * feat: reduce `LsMaxRsDeq` to 2 and delete it * feat: support one load/store pipeline * feat: parameterize `EnsbufferWidth` * chore: resharp codes for better generated name * top-down: add initial top-down features * rob600: enlarge queue/buffer size * top-down: add l1, l2, l3 and ddr loads bound perf counters * top-down: dig into l1d loads bound * top-down: move memory related counters to `Scheduler` * top-down: add 2 Ldus and 2 Stus * top-down: v1.0 * huancun: bump HuanCun to a version with top-down * chore: restore parameters and update `build.sc` * top-down: use ExcitingUtils instead of BoringUtils * top-down: add switch of top-down counters * top-down: add top-down scripts * difftest: enlarge stuck limit cycles again Co-authored-by: gaozeyu <[email protected]> show more ... /XiangShan/Makefile /XiangShan/README.md /XiangShan/build.sc /XiangShan/readme.zh-cn.md /XiangShan/scripts/top-down/.gitignore /XiangShan/scripts/top-down/README.md /XiangShan/scripts/top-down/file.f /XiangShan/scripts/top-down/json2f.py /XiangShan/scripts/top-down/run_emu.sh /XiangShan/scripts/top-down/top-down.sh /XiangShan/scripts/top-down/top_down.py /XiangShan/scripts/top-down/xsrun /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/utils/DataModuleTemplate.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/utils/SRAMTemplate.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala Rename.scala /XiangShan/src/main/scala/xiangshan/cache/CacheInstruction.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Composer.scala /XiangShan/src/main/scala/xiangshan/frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/frontend/FauFTB.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/WrBypass.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ReplacePipe.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
ccfddc82	01-Nov-2022	Haojin Tang <[email protected]>	rename: Re-rename instead of walking back after redirect (#1768) * freelist & refcounter: implement arch states * walk: restore and walk again when redirecting * ROB: optimize invalidation of rename: Re-rename instead of walking back after redirect (#1768) * freelist & refcounter: implement arch states * walk: restore and walk again when redirecting * ROB: optimize invalidation of `valid` show more ... /XiangShan/.github/workflows/emu.yml /XiangShan/README.md /XiangShan/difftest /XiangShan/huancun /XiangShan/readme.zh-cn.md /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/device/AXI4Memory.scala /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/Hold.scala /XiangShan/src/main/scala/utils/PipelineConnect.scala /XiangShan/src/main/scala/utils/RegMap.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FUBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/InputBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/issue/BypassNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/PayloadArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/issue/SelectPolicy.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala Rename.scala RenameTable.scala freelist/BaseFreeList.scala freelist/MEFreeList.scala freelist/RefCounter.scala freelist/StdFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/FakeDCache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AtomicsReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/AsynchronousMetaArray.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLBMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/top/SimTop.scala
6474c47f	14-Jul-2022	Yinan Xu <[email protected]>	rob: optimize timing for commit and walk (#1644) * rob: separate walk and commit valid bits * rob: optimize instrCnt timing * rob: fix blockCommit condition when flushPipe When flushPipe is rob: optimize timing for commit and walk (#1644) * rob: separate walk and commit valid bits * rob: optimize instrCnt timing * rob: fix blockCommit condition when flushPipe When flushPipe is enabled, it will block commits in ROB. However, in the deqPtrModule, the commit is not blocked. This commit fixes the issue. show more ... /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/utils/CircularQueuePtr.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala Rename.scala RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala
f025d715	13-Jul-2022	Yinan Xu <[email protected]>	decode: move the soft-prefetch decoder to rename (#1646) This commit moves the decoder of software prefetch instructions to the rename stage. Previously the decoding of software prefetch instruc decode: move the soft-prefetch decoder to rename (#1646) This commit moves the decoder of software prefetch instructions to the rename stage. Previously the decoding of software prefetch instructions affects the imm gen and causes a long critical path. show more ... /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala Rename.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
66b2c4a4	12-Jul-2022	Yinan Xu <[email protected]>	ctrl: optimize freelist timing (#1633) * rat: map all arch registers to zero when init * freelist: fix stepBack width * freelist: fix timing of free offset /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/ParallelMux.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/issue/SelectPolicy.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala RenameTable.scala freelist/MEFreeList.scala freelist/RefCounter.scala freelist/StdFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/test/scala/top/SimMMIO.scala
0febc381	09-Jul-2022	Yinan Xu <[email protected]>	decode: move fusion decoder result Mux to rename (#1631) This commit moves the fusion decoder to both decode and rename stage. In the decode stage, fusion decoder determines whether the instructi decode: move fusion decoder result Mux to rename (#1631) This commit moves the fusion decoder to both decode and rename stage. In the decode stage, fusion decoder determines whether the instruction pairs can be fused. Valid bits of decode are not affected by fusion decoder. This should fix the timing issues of rename.valid. In the rename stage, some fields are updated according the result of fusion decoder. This will bring a minor timing path to both valid and other fields in uop in the rename stage. However, since freelist and rat have worse timing. This should not cause timing issues. show more ... /XiangShan/build.sc /XiangShan/src/main/scala/utils/PerfCounterUtils.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala Rename.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala /XiangShan/src/main/scala/xiangshan/package.scala
c51eab43	06-Jul-2022	Yinan Xu <[email protected]>	rob: add separated optimized walk valid bits (#1614) Some modules rely on the walk valid bits of ROB. This commit optimizes the timing by providing separated walk valid bits, which is far better t rob: add separated optimized walk valid bits (#1614) Some modules rely on the walk valid bits of ROB. This commit optimizes the timing by providing separated walk valid bits, which is far better than the commit valid bits. show more ... /XiangShan/src/main/scala/xiangshan/Bundle.scala Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
00210c34	06-Jul-2022	Yinan Xu <[email protected]>	dpq: optimize read and write timing of data module (#1610) This commit changes the data modules in Dispatch Queue. We use one-hot indices to read and write the data array. /XiangShan/difftest /XiangShan/src/main/scala/utils/CircularQueuePtr.scala /XiangShan/src/main/scala/utils/PipelineConnect.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Rs.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala freelist/BaseFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AtomicsReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/RefillPipe.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/package.scala
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