issue - OpenGrok history log for /XiangShan/src/main/scala/xiangshan/backend/issue

Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
ab6e9afa	22-Jun-2020	jinyue <[email protected]>	Merge branch 'issuequeue-data' into issuequeue IssueQueue.scala
400fcd9f	22-Jun-2020	jinyue <[email protected]>	IssueQueue.scala add Redirect Logic for branch miss and exception IssueQueue.scala
35c1d187	22-Jun-2020	ZhangZifei <[email protected]>	IssueQueue: optimize listen/bypass coding-style(space for time) IssueQueue.scala
4f0e139e	22-Jun-2020	ZhangZifei <[email protected]>	IssueQueue: replace listen/bypass's logic to ParallelOR/MUX IssueQueue.scala
1a05278c	22-Jun-2020	jinyue <[email protected]>	Merge branch 'issuequeue-data' into issuequeue merge branch issuequeue-data with newest change /XiangShan/src/main/scala/xiangshan/backend/Backend.scala IssueQueue.scala
10721ce6	22-Jun-2020	jinyue <[email protected]>	IssueQueue.scala: add dequeue logic, out.direct need to do. IssueQueue.scala
7003bf16	22-Jun-2020	jinyue <[email protected]>	IssueQueue.scala: change the way of CCU to reduce the latency IssueQueue.scala
ad55d194	22-Jun-2020	ZhangZifei <[email protected]>	IssueQueue: remove io.bypassDatas bypassDatas is confilct with wakeUpPorts(CDB) /XiangShan/src/main/scala/xiangshan/backend/Backend.scala IssueQueue.scala
e71f3325	22-Jun-2020	jinyue <[email protected]>	Merge branch 'issuequeue-data' into issuequeue merge issuequeue-data with gramma change & add listen to CDB logic IssueQueue.scala
8879c7d4	22-Jun-2020	ZhangZifei <[email protected]>	IssueQueue: add byPass listening byPass is only from ALUIQ to ALUIQ IssueQueue.scala
60d28aaa	21-Jun-2020	ZhangZifei <[email protected]>	IssueQueue: add data part. from regfile and listen to CDB also enable src3Data/src3Rdy/psrc3... IssueQueue.scala
9f93c361	21-Jun-2020	ZhangZifei <[email protected]>	IssueQueue: fix some syntax bugs and change some signals' name IssueQueue.scala
7b95ae63	21-Jun-2020	jinyue <[email protected]>	IssueQueue.scala: fix some grammar mistakes IssueQueue.scala
877c2d47	21-Jun-2020	jinyue <[email protected]>	IssueQueue.scala:add Select Circuit /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
71d5424c	21-Jun-2020	jinyue <[email protected]>	IssueQueue.scala: add tag queue enqueue logic IssueQueue.scala
7026d899	21-Jun-2020	jinyue <[email protected]>	IsssueQueue.scala: add tag queue and data queue as issue queue content /XiangShan/.github/workflows/core_ci.yml /XiangShan/Makefile /XiangShan/fpga/board/axu3cg/constr/hdmi.xdc /XiangShan/fpga/board/axu3cg/rtl/system_top.v /XiangShan/src/main/scala/xiangshan/Bundle.scala IssueQueue.scala /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/ram.cpp
296e7422	19-Jun-2020	LinJiawei <[email protected]>	Add roq walk signal. Fix issue queue bypass logic. /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala IssueQueue.scala
9a2e6b8a	18-Jun-2020	LinJiawei <[email protected]>	Adjust pipeline, refactor EXU, IssueQueue /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/package.scala
5844fcf0	16-Jun-2020	LinJiawei <[email protected]>	Initially completed the module interface design /XiangShan/.gitignore /XiangShan/Makefile /XiangShan/README.md /XiangShan/build.sbt /XiangShan/build.sc /XiangShan/debug/.gitignore /XiangShan/debug/Makefile /XiangShan/devlog.md /XiangShan/fpga/Makefile /XiangShan/fpga/Makefile.check /XiangShan/fpga/board/axu3cg/bd/prm.tcl /XiangShan/fpga/board/axu3cg/constr/hdmi.xdc /XiangShan/fpga/board/axu3cg/mk.tcl /XiangShan/fpga/board/axu3cg/rtl/addr_mapper.v /XiangShan/fpga/board/axu3cg/rtl/hdmi/i2c_config.v /XiangShan/fpga/board/axu3cg/rtl/hdmi/i2c_master_bit_ctrl.v /XiangShan/fpga/board/axu3cg/rtl/hdmi/i2c_master_byte_ctrl.v /XiangShan/fpga/board/axu3cg/rtl/hdmi/i2c_master_defines.v /XiangShan/fpga/board/axu3cg/rtl/hdmi/i2c_master_top.v /XiangShan/fpga/board/axu3cg/rtl/hdmi/timescale.v /XiangShan/fpga/board/axu3cg/rtl/system_top.v /XiangShan/fpga/board/common.tcl /XiangShan/fpga/board/ultraZ/bd/prm.tcl /XiangShan/fpga/board/ultraZ/constr/constr.xdc /XiangShan/fpga/board/ultraZ/mk.tcl /XiangShan/fpga/board/ultraZ/rtl/addr_mapper.v /XiangShan/fpga/board/ultraZ/rtl/system_top.v /XiangShan/fpga/board/zedboard/bd/prm.tcl /XiangShan/fpga/board/zedboard/constr/constr.xdc /XiangShan/fpga/board/zedboard/constr/vga.xdc /XiangShan/fpga/board/zedboard/mk.tcl /XiangShan/fpga/board/zedboard/rtl/addr_mapper.v /XiangShan/fpga/board/zedboard/rtl/system_top.v /XiangShan/fpga/boot/.gitignore /XiangShan/fpga/boot/README.md /XiangShan/fpga/boot/axu3cg/u-boot.elf /XiangShan/fpga/boot/bootgen-zynq.bif /XiangShan/fpga/boot/bootgen-zynqmp.bif /XiangShan/fpga/boot/bug-list.md /XiangShan/fpga/boot/mk.tcl /XiangShan/fpga/lib/include/axi.vh /XiangShan/fpga/noop.tcl /XiangShan/fpga/resource/ddr-loader/ddr-loader.c /XiangShan/project/build.properties /XiangShan/scalastyle-config.xml /XiangShan/scalastyle-test-config.xml /XiangShan/scripts/vlsi_mem_gen /XiangShan/src/main/scala/bus/axi4/AXI4.scala /XiangShan/src/main/scala/bus/axi4/Delayer.scala /XiangShan/src/main/scala/bus/simplebus/Crossbar.scala /XiangShan/src/main/scala/bus/simplebus/DistributedMem.scala /XiangShan/src/main/scala/bus/simplebus/SimpleBus.scala /XiangShan/src/main/scala/bus/simplebus/ToAXI4.scala /XiangShan/src/main/scala/device/AXI4DummySD.scala /XiangShan/src/main/scala/device/AXI4Flash.scala /XiangShan/src/main/scala/device/AXI4Keyboard.scala /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/device/AXI4Slave.scala /XiangShan/src/main/scala/device/AXI4Timer.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/device/AXI4VGA.scala /XiangShan/src/main/scala/fpu/Classify.scala /XiangShan/src/main/scala/fpu/F32toF64.scala /XiangShan/src/main/scala/fpu/F64toF32.scala /XiangShan/src/main/scala/fpu/FCMP.scala /XiangShan/src/main/scala/fpu/FMV.scala /XiangShan/src/main/scala/fpu/FPUSubModule.scala /XiangShan/src/main/scala/fpu/FloatToInt.scala /XiangShan/src/main/scala/fpu/IntToFloat.scala /XiangShan/src/main/scala/fpu/README.md /XiangShan/src/main/scala/fpu/RoundingUnit.scala /XiangShan/src/main/scala/fpu/divsqrt/DivSqrt.scala /XiangShan/src/main/scala/fpu/divsqrt/MantDivSqrt.scala /XiangShan/src/main/scala/fpu/divsqrt/OnTheFlyConv.scala /XiangShan/src/main/scala/fpu/divsqrt/SrtTable.scala /XiangShan/src/main/scala/fpu/fma/ArrayMultiplier.scala /XiangShan/src/main/scala/fpu/fma/FMA.scala /XiangShan/src/main/scala/fpu/fma/LZA.scala /XiangShan/src/main/scala/fpu/package.scala /XiangShan/src/main/scala/fpu/util/CarrySaveAdder.scala /XiangShan/src/main/scala/fpu/util/FPUDebug.scala /XiangShan/src/main/scala/fpu/util/ORTree.scala /XiangShan/src/main/scala/fpu/util/ShiftLeftJam.scala /XiangShan/src/main/scala/fpu/util/ShiftRightJam.scala /XiangShan/src/main/scala/gpu/GPU.scala /XiangShan/src/main/scala/noop/BPU.scala /XiangShan/src/main/scala/noop/Bundle.scala /XiangShan/src/main/scala/noop/Cache.scala /XiangShan/src/main/scala/noop/Decode.scala /XiangShan/src/main/scala/noop/EXU.scala /XiangShan/src/main/scala/noop/IDU1.scala /XiangShan/src/main/scala/noop/IDU2.scala /XiangShan/src/main/scala/noop/IFU.scala /XiangShan/src/main/scala/noop/ISU.scala /XiangShan/src/main/scala/noop/NOOP.scala /XiangShan/src/main/scala/noop/NOOPTrap.scala /XiangShan/src/main/scala/noop/TLB.scala /XiangShan/src/main/scala/noop/WBU.scala /XiangShan/src/main/scala/noop/fu/ALU.scala /XiangShan/src/main/scala/noop/fu/CSR.scala /XiangShan/src/main/scala/noop/fu/FPU.scala /XiangShan/src/main/scala/noop/fu/LSU.scala /XiangShan/src/main/scala/noop/fu/MDU.scala /XiangShan/src/main/scala/noop/fu/MOU.scala /XiangShan/src/main/scala/noop/isa/Priviledged.scala /XiangShan/src/main/scala/noop/isa/RVA.scala /XiangShan/src/main/scala/noop/isa/RVC.scala /XiangShan/src/main/scala/noop/isa/RVD.scala /XiangShan/src/main/scala/noop/isa/RVF.scala /XiangShan/src/main/scala/noop/isa/RVI.scala /XiangShan/src/main/scala/noop/isa/RVM.scala /XiangShan/src/main/scala/noop/isa/RVZicsr.scala /XiangShan/src/main/scala/noop/isa/RVZifencei.scala /XiangShan/src/main/scala/system/Coherence.scala /XiangShan/src/main/scala/system/Prefetcher.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/TopMain.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/Debug.scala /XiangShan/src/main/scala/utils/FlushableQueue.scala /XiangShan/src/main/scala/utils/GTimer.scala /XiangShan/src/main/scala/utils/Hold.scala /XiangShan/src/main/scala/utils/LFSR64.scala /XiangShan/src/main/scala/utils/LatencyPipe.scala /XiangShan/src/main/scala/utils/Lock.scala /XiangShan/src/main/scala/utils/LookupTree.scala /XiangShan/src/main/scala/utils/Pipeline.scala /XiangShan/src/main/scala/utils/RegMap.scala /XiangShan/src/main/scala/utils/SRAMTemplate.scala /XiangShan/src/main/scala/utils/StopWatch.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala IssueStage.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeIFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/utils/BitUtils.scala /XiangShan/src/main/scala/xiangshan/utils/Debug.scala /XiangShan/src/main/scala/xiangshan/utils/FlushableQueue.scala /XiangShan/src/main/scala/xiangshan/utils/GTimer.scala /XiangShan/src/main/scala/xiangshan/utils/Hold.scala /XiangShan/src/main/scala/xiangshan/utils/LFSR64.scala /XiangShan/src/main/scala/xiangshan/utils/LatencyPipe.scala /XiangShan/src/main/scala/xiangshan/utils/Lock.scala /XiangShan/src/main/scala/xiangshan/utils/LookupTree.scala /XiangShan/src/main/scala/xiangshan/utils/ParallelMux.scala /XiangShan/src/main/scala/xiangshan/utils/Pipeline.scala /XiangShan/src/main/scala/xiangshan/utils/RegMap.scala /XiangShan/src/main/scala/xiangshan/utils/SRAMTemplate.scala /XiangShan/src/main/scala/xiangshan/utils/StopWatch.scala /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/device.cpp /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/keyboard.cpp /XiangShan/src/test/csrc/macro.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/monitor.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/sdcard.cpp /XiangShan/src/test/csrc/uart.cpp /XiangShan/src/test/csrc/vga.cpp /XiangShan/src/test/scala/cache/CacheTest.scala /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/vsrc/monitor.v /XiangShan/src/test/vsrc/ram.v /XiangShan/tools/readmemh/Makefile /XiangShan/tools/readmemh/gen-treadle-readmemh.c /XiangShan/tools/readmemh/groupby-4byte.c /XiangShan/tools/readmemh/split-readmemh.c
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