issue - OpenGrok history log for /XiangShan/src/main/scala/xiangshan/backend/issue

Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
e1a85e9f	05-Jul-2024	chengguanghui <[email protected]>	PerfEvent: refactor perfevents in Backend * add `dispatch2Iq_out_fire_cnt`, `issueQueue_enq_fire_cnt`, `issueQueue_full` event in scheduler * add busytable event * move collecting perfevents from PerfEvent: refactor perfevents in Backend * add `dispatch2Iq_out_fire_cnt`, `issueQueue_enq_fire_cnt`, `issueQueue_full` event in scheduler * add busytable event * move collecting perfevents from `ctrlBlock` to `backend` * change `perfEventsCtrl` into `perfEventsBackend` show more ... /XiangShan/build.sc /XiangShan/macros/src/main/scala/CSRMacros.scala /XiangShan/src/main/resources/aia /XiangShan/src/main/resources/vsrc/cmip_dff_sync.sv /XiangShan/src/main/resources/vsrc/imsic/imsic_csr_gate.v /XiangShan/src/main/resources/vsrc/imsic/imsic_csr_reg.v /XiangShan/src/main/resources/vsrc/imsic/imsic_csr_top.v /XiangShan/src/main/scala/device/IMSIC.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/GPAMem.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/PseudoInstruction.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAnnotation.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundle.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRCustom.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/DretEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MretEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/SretEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryDEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRFields.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRNamedConstant.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPMP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/ExceptionBundle.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptBundle.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/PMPEntryModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SstcInterruptGen.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/StateEnBundle.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SupervisorLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/VirtualSupervisorLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/Trigger.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/xiangshan/backend/BackendMain.scala
ae0295f4	16-Jul-2024	Tang Haojin <[email protected]>	chore: bump chisel 6.5.0 (#3210) /XiangShan/.github/workflows/emu.yml /XiangShan/build.sc /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/xiangshan/backend/Backend.scala Entries.scala EntryBundles.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/yunsuan
ac90e54a	16-Jul-2024	xiaofeibao-xjtu <[email protected]>	IssueQueue: fix bug of segment instruction which lqidx and sqidx are same (#3205) /XiangShan/.github/workflows/emu.yml /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala EntryBundles.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala /XiangShan/src/main/scala/xiangshan/package.scala
bb2f3f51	12-Jul-2024	Tang Haojin <[email protected]>	perf: use perfUtils in `Utility` (#3190) Currently, log and perf utilities such as `XSPerfAccumulate` are implemented in many repositories like XiangShan, CoupledL2 and HuanCun. This PR unifies th perf: use perfUtils in `Utility` (#3190) Currently, log and perf utilities such as `XSPerfAccumulate` are implemented in many repositories like XiangShan, CoupledL2 and HuanCun. This PR unifies them and put them in Utility repository. show more ... /XiangShan/.github/workflows/emu.yml /XiangShan/coupledL2 /XiangShan/huancun /XiangShan/openLLC /XiangShan/src/chisel/main/scala/xiangshan/transforms/PrintModuleName.scala /XiangShan/src/chisel3/main/scala/xiangshan/transforms/PrintModuleName.scala /XiangShan/src/main/scala/device/AXI4Memory.scala /XiangShan/src/main/scala/device/AXI4Plic.scala /XiangShan/src/main/scala/device/TLTimer.scala /XiangShan/src/main/scala/device/standalone/StandAloneDevice.scala /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/BusPerfMonitor.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/top/XSNoCTop.scala /XiangShan/src/main/scala/utils/DebugIdentityNode.scala /XiangShan/src/main/scala/utils/PerfCounterUtils.scala /XiangShan/src/main/scala/utils/TLDump.scala /XiangShan/src/main/scala/utils/Trigger.scala /XiangShan/src/main/scala/xiangshan/L2Top.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/RFReadArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2IqFpImp.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Bku.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/ByteMaskTailGen.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FALU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FCVT.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIDiv.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VPPU.scala DataArray.scala Dispatch2Iq.scala EntryBundles.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Snapshot.scala /XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/AbstractDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AtomicsReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/storepipe/StorePipe.scala /XiangShan/src/main/scala/xiangshan/cache/wpu/WPU.scala /XiangShan/src/main/scala/xiangshan/cache/wpu/WPUWrapper.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala /XiangShan/utility
28ac1c16	12-Jul-2024	xiaofeibao-xjtu <[email protected]>	Backend & MemBlock: feedback use lqidx instead of robidx for fix timing and fix bug of vld feedback (#3189) /XiangShan/coupledL2 /XiangShan/src/main/scala/device/standalone/StandAloneDevice.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala Entries.scala EntryBundles.scala IssueBlockParams.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala /XiangShan/yunsuan
38f78b5d	10-Jul-2024	xiaofeibao-xjtu <[email protected]>	Backend&MemBlock: feedback use sqidx instead of robidx and uopidx for fix timing (#3172) /XiangShan/.github/workflows/emu.yml /XiangShan/.gitmodules /XiangShan/Makefile /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/scripts/xiangshan.py /XiangShan/src/main/resources/aia /XiangShan/src/main/scala/device/imsic_axi_top.scala /XiangShan/src/main/scala/device/standalone/StandAloneCLINT.scala /XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala /XiangShan/src/main/scala/device/standalone/StandAloneDevice.scala /XiangShan/src/main/scala/device/standalone/StandAlonePLIC.scala /XiangShan/src/main/scala/device/standalone/standalone_device.mk /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/top/XSNoCTop.scala /XiangShan/src/main/scala/utils/AXI4Lite.scala /XiangShan/src/main/scala/utils/VerilogAXI4LiteRecord.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Vsetu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala Entries.scala EntryBundles.scala IssueBlockParams.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala /XiangShan/src/main/scala/xiangshan/backend/rob/RobDeqPtrWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala /XiangShan/utility /XiangShan/yunsuan
7a9ea6c5	01-Jul-2024	Anzooooo <[email protected]>	Dispatch2Iq: fix timing problem caused by bit width in 'Dispatch2iq'. /XiangShan/.github/workflows/emu.yml /XiangShan/.gitmodules /XiangShan/Makefile /XiangShan/build.sc /XiangShan/coupledL2 /XiangShan/openLLC /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/BusPerfMonitor.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/xiangshan/L2Top.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/PipeGroupConnect.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Vsetu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/yunsuan
b9631a81	02-Jul-2024	xiaofeibao-xjtu <[email protected]>	IssueQueue: change othersTransPolicy when allComp or allSimp for fix timing (#3120) /XiangShan/.github/workflows/check_verilog.py /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/utils/VerilogAXI4Record.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala Entries.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/yunsuan
195ef4a5	28-Jun-2024	Tang Haojin <[email protected]>	build: bump chisel 3.6.1, scala 2.13.14, mill 0.11.8, etc. (#3118) /XiangShan/.mill-version /XiangShan/build.sc /XiangShan/rocket-chip /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Composer.scala /XiangShan/src/main/scala/xiangshan/frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/FIFO.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/xiangshan/XSTester.scala
91f31488	26-Jun-2024	xiaofeibao-xjtu <[email protected]>	Backend: remove loadCancel from dispatch2iq to enqEntry for fix timing (#3105) EnqEntry.scala Entries.scala EntryBundles.scala IssueQueue.scala
d77cf63c	26-Jun-2024	xiaofeibao-xjtu <[email protected]>	Backend: remove calculate numLsElem from dispatch2iq to rename /XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
9ff64fb6	24-Jun-2024	Anzooooo <[email protected]>	VLSU: Change the maximum number of 'numLsElem' dispatch by 'dispatch2iq'. For emulation on Palladium, now the maximum 'numLsElem' number that can be emitted per port is: 16 2 2 2 2 2. So vector i VLSU: Change the maximum number of 'numLsElem' dispatch by 'dispatch2iq'. For emulation on Palladium, now the maximum 'numLsElem' number that can be emitted per port is: 16 2 2 2 2 2. So vector instructions other than 'unit-stride' can only be issued on the first port. Scalars and 'unit-stride' instruction can be emitted at either port if the 'Lsq' allows allocation. show more ... /XiangShan/coupledL2 /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/Og2ForVector.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/yunsuan
dd40a82b	20-Jun-2024	sinsanction <[email protected]>	Entries: optimize timing of mem IQs' response signals (#3088) /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala Entries.scala EntryBundles.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala /XiangShan/src/main/scala/xiangshan/frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
864480f4	18-Jun-2024	xiaofeibao-xjtu <[email protected]>	BypassNetwork: ExuOH->ExuVec, add mask for forwardOrBypassValidVec3 (#3083) /XiangShan/.github/workflows/emu.yml /XiangShan/.github/workflows/nightly.yml /XiangShan/Makefile /XiangShan/difftest /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala EnqEntry.scala Entries.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/cache/CacheInstruction.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/AbstractDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/storepipe/StorePipe.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Composer.scala /XiangShan/src/main/scala/xiangshan/frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/frontend/FauFTB.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StreamPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala /XiangShan/utility
ee8d1f1b	14-Jun-2024	sinsanction <[email protected]>	IssueQueue: when src0-2 read vector reg #0, transfer to src3 to read v0 (#3060) /XiangShan/.github/CODEOWNERS /XiangShan/.github/ISSUE_TEMPLATE/1-bug_report.yml /XiangShan/.github/ISSUE_TEMPLATE/2-feature_request.yaml /XiangShan/.github/ISSUE_TEMPLATE/3-problem.yaml /XiangShan/.github/ISSUE_TEMPLATE/4-other_question.yml /XiangShan/.github/filters.yaml /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
dd461822	12-Jun-2024	sinsanction <[email protected]>	IssueQueueMemAddrImp: only wen signals for data types that load IQ will write back can be sent out IssueBlockParams.scala IssueQueue.scala
399ac7a1	11-Jun-2024	sinsanction <[email protected]>	IssueBlockParams: check the type of read operands when generating the WB waking up ports IssueBlockParams.scala
17f99999	11-Jun-2024	sinsanction <[email protected]>	Dispatch2IqImp: generate busytable read ports based on the actual number of read operands required /XiangShan/.github/filters.yaml /XiangShan/.github/workflows/emu.yml /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntFPToVec.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/DivUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/JumpUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/MulUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIDiv.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VPPU.scala Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/FreeList.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/utility /XiangShan/yunsuan
29aa55c1	03-Jun-2024	xiaofeibao <[email protected]>	ResetPregStateReq: add isV0 isVl /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
b38000bf	30-May-2024	sinsanction <[email protected]>	IssueQueueIO: move v0 reading request of src0-2 to src3 IssueQueue.scala
e82613f6	30-May-2024	sinsanction <[email protected]>	Dispatch2Iq: fix connection of readVfState /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataConfig.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataSource.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/RFReadArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/RFWBConflictChecker.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiterParams.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbConfig.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbFuBusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntFPToVec.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
463e0005	29-May-2024	sinsanction <[email protected]>	Dispatch2Iq: fix connection of readVfState Dispatch2Iq.scala
09182486	29-May-2024	sinsanction <[email protected]>	Dispatch2Iq: fix signal connection /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2IqFpImp.scala Dispatch2Iq.scala
64ed309c	29-May-2024	sinsanction <[email protected]>	Dispatch2Iq: move the connection of uopsIn to base class Dispatch2Iq.scala
07b5cc60	29-May-2024	xiaofeibao <[email protected]>	Backend: change MaskSrcData VConfigData to V0Data VlData /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataConfig.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/RdConfig.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/PregParams.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala
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