misc: update PCL information (#899)

XiangShan is jointly released by ICT and PCL.

backend,rs: add isFirstIssue flags in status entries (#888)

scheduler: add support for parameterization via rs and dp ports (#882)

This commit adds support for a parameterized scheduler. A scheduler
can be parameterized via issue and dispatch ports.

Note

scheduler: add support for parameterization via rs and dp ports (#882)

This commit adds support for a parameterized scheduler. A scheduler
can be parameterized via issue and dispatch ports.

Note: other parameters have not been tested.

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backend: wrap all RS into a larger scheduler module (#880)

This commit adds an non-parameterized scheduler containing all reservation stations.
Now IntegerBlock, FloatBlock, MemBlock contain only f

backend: wrap all RS into a larger scheduler module (#880)

This commit adds an non-parameterized scheduler containing all reservation stations.
Now IntegerBlock, FloatBlock, MemBlock contain only function units.
The Schduler connects dispatch with all function units.
Parameterization to be added later.

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backend: optimize dispatch and issue timing (#821)

* better select policy timing
* unified RS enqueue ports for 4 ALUs
* wrap imm extractor into a module
* backend,rs: wrap dataArray in RawDataMo

backend: optimize dispatch and issue timing (#821)

* better select policy timing
* unified RS enqueue ports for 4 ALUs
* wrap imm extractor into a module
* backend,rs: wrap dataArray in RawDataModuleTemplate
* should only bypass data between the same addr when allocate.valid

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Add MulanPSL-2.0 License (#824)

In this commit, we add License for XiangShan project.

backend, rs: support multiple enqueue and dequeue instructions (#820)

* backend,RS: add numEnq parameter to allow multiple enqueue instructions

* backend,RS: support multiple issue instructions a

backend, rs: support multiple enqueue and dequeue instructions (#820)

* backend,RS: add numEnq parameter to allow multiple enqueue instructions

* backend,RS: support multiple issue instructions at each cycle

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backend,RS: rewrite RS to optimize timing (#812)

* test,vcs: call $finish when difftest fails

* backend,RS: refactor with more submodules

This commit rewrites the reservation station in a more

backend,RS: rewrite RS to optimize timing (#812)

* test,vcs: call $finish when difftest fails

* backend,RS: refactor with more submodules

This commit rewrites the reservation station in a more configurable style.

The new RS has not finished.
- Support only integer instructions
- Feedback from load/store instructions is not supported
- Fast wakeup for multi-cycle instructions is not supported
- Submodules are refined later

* RS: use wakeup signals from arbiter.out

* RS: support feedback and re-schedule when needed

For load and store reservation stations, the instructions that left RS before may be
replayed later.

* test,vcs: check difftest_state and return on nemu trap instructions

* backend,RS: support floating-point operands and delayed regfile read for store RS

This commit adds support for floating-point instructions in reservation stations.
Beside, currently fp data for store operands come a cycle later than int data. This
feature is also supported.

Currently the RS should be ready for any circumstances.

* rs,status: don't trigger assertions when !status.valid

* test,vcs: add +workload option to specify the ram init file

* backend,rs: don't enqueue when redirect.valid or flush.valid

* backend,rs: support wait bit that instruction waits until store issues

This commit adds support for wait bit, which is mainly used in load and
store reservation stations to delay instruction issue until the corresponding
store instruction issued.

* backend,RS: optimize timing

This commit optimizes BypassNetwork and PayloadArray timing.

- duplicate bypass mask to avoid too many FO4
- use one-hot vec to get read data

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backend,mem: add Store Sets memory dependence predictor (#796)

* LoadQueue: send stFtqIdx via rollback request

* It will make it possible for setore set to update its SSIT

* StoreSet: setup st

backend,mem: add Store Sets memory dependence predictor (#796)

* LoadQueue: send stFtqIdx via rollback request

* It will make it possible for setore set to update its SSIT

* StoreSet: setup store set update req

* StoreSet: add store set identifier table (SSIT)

* StoreSet: add last fetched store table (LFST)

* StoreSet: put SSIT into decode stage

* StoreSet: put LFST into dispatch1

* Future work: optimize timing

* RS: store rs now supports delayed issue

* StoreSet: add perf counter

* StoreSet: fix SSIT update logic

* StoreSet: delay LFST update input for 1 cycle

* StoreSet: fix LFST update logic

* StoreSet: fix LFST raddr width

* StoreSet: do not force store in ss issue in order

Classic store set requires store in the same store set issue in seq.
However, in current micro-architecture, such restrict will lead to
severe perf lost. We choose to disable it until we find another way
to fix it.

* StoreSet: support ooo store in the same store set

* StoreSet: fix store set merge logic

* StoreSet: check earlier store when read LFST

* If store-load pair is in the same dispatch bundle, loadWaitBit should
also be set for load

* StoreSet: increase default SSIT flush period

* StoreSet: fix LFST read logic

* Fix commit c0e541d14

* StoreSet: add StoreSetEnable parameter

* RSFeedback: add source type

* StoreQueue: split store addr and store data

* StoreQueue: update ls forward logic

* Now it supports splited addr and data

* Chore: force assign name for load/store unit

* RS: add rs'support for store a-d split

* StoreQueue: fix stlf logic

* StoreQueue: fix addr wb sq update logic

* AtomicsUnit: support splited a/d

* Parameters: disable store set by default

* WaitTable: wait table will not cause store delay

* WaitTable: recover default reset period to 2^17

* Fix dev-stad merge conflict

* StoreSet: enable storeset

* RS: disable store rs delay logic

CI perf shows that current delay logic will cause perf loss. Disable
unnecessary delay logic will help.

To be more specific, `io.readyVec` caused the problem. It will be
updated in future commits.

* RS: opt select logic with load delay (ldWait)

* StoreSet: disable 2-bit lwt

Co-authored-by: ZhangZifei <[email protected]>

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bundle: use Vec for src in ExuInput (#805)

This commit replaces src1, src2, src3 in Bundle ExuInput with Vec(3, UInt).
Should be easier for RS.

Backend: add mul to fast wakeup (#769)

* [WIP] Backend: add mul to fast wake-up

* Backend: handle mul wb priority and fix wrong delay

* RS: devide fastwakeup and nonBlocked(they were binded)

bundle,uop: use Vec for lsrc, psrc, srcState and srcType (#797)

This commit uses Vec for lsrc, psrc, srcState and srcType in MicroOp bundle.
This makes uop easier to access.

MemBlock: split store addr and store data (#781)

* RSFeedback: add source type

* StoreQueue: split store addr and store data

* StoreQueue: update ls forward logic

* Now it supports splited

MemBlock: split store addr and store data (#781)

* RSFeedback: add source type

* StoreQueue: split store addr and store data

* StoreQueue: update ls forward logic

* Now it supports splited addr and data

* Chore: force assign name for load/store unit

* RS: add rs'support for store a-d split

* StoreQueue: fix stlf logic

* StoreQueue: fix addr wb sq update logic

* AtomicsUnit: support splited a/d

* StoreQueue: add sbuffer enq condition assertion

Store data op (std) may still be invalid after store addr op's (sta)
commitment, so datavalid needs to be checked before commiting
store data to sbuffer

Note that at current commit a non-completed std op for a
commited store may exist. We should make sure that uop
will not be cancelled by a latter branch mispredict. More work
to be done!

* Roq: add std/sta split writeback logic

Now store will commit only if both sta & std have been writebacked

Co-authored-by: ZhangZifei <[email protected]>

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Perf: add perf counter to record rs wake up source (#792)

RS: fix mixed usage of ISSQUESIZE and iqSize (#764)

Co-authored-by: ZhangZifei <[email protected]>

Refactor parameters, SimTop and difftest (#753)

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's

Refactor parameters, SimTop and difftest (#753)

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's manual, DPI-C calls should be more efficient than accessing from dut_ptr.
(2) DPI-C is cross-platform (Verilator, VCS, ...)
(3) difftest APIs are splited from emu.cpp to possibly support more backend platforms
(NEMU, Spike, ...)

The performance at this commit is quite slower than the original emu.
Performance issues will be fixed later.

* [WIP] SimTop: try to use 'XSTop' as soc

* CircularQueuePtr: ues F-bounded polymorphis instead implict helper

* Refactor parameters & Clean up code

* difftest: support basic difftest

* Support diffetst in new sim top

* Difftest; convert recode fmt to ieee754 when comparing fp regs

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Debug: add int/exc inst wb to debug queue

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Difftest: fix naive commit num limit

Co-authored-by: Yinan Xu <[email protected]>
Co-authored-by: William Wang <[email protected]>

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CircularQueuePtr: use F-bounded polymorphism instead of implicit helper (#750)

Merge branch 'master' of github.com:RISCVERS/XiangShan

RS: fix bug that fp src's flushed enqueue conflicts with next enqueue (#715)

* RS: fix bug that fp src's flushed enqueue conflicts with next enqueue

* RS: fix bug that ctrl's flushed enqueue conf

RS: fix bug that fp src's flushed enqueue conflicts with next enqueue (#715)

* RS: fix bug that fp src's flushed enqueue conflicts with next enqueue

* RS: fix bug that ctrl's flushed enqueue conflicts with next enqueue

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Refactor XSPerf, now we have three XSPerf Functions.
XSPerfAccumulate: sum up performance values.
XSPerfHistogram: count the occurrence of performance values, split them
into bins, so that we can est

Refactor XSPerf, now we have three XSPerf Functions.
XSPerfAccumulate: sum up performance values.
XSPerfHistogram: count the occurrence of performance values, split them
into bins, so that we can estimate their distribution.
XSPerfMax: get max of performance values.

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Perf: add queue perf analysis utility (#714)

* perf: set acc arg of XSPerf as false by default

* perf: add write-port competition counter for intBlock & floatBlock

* perf: remove prefix of per

Perf: add queue perf analysis utility (#714)

* perf: set acc arg of XSPerf as false by default

* perf: add write-port competition counter for intBlock & floatBlock

* perf: remove prefix of perf signal

* perf: add perf-cnt for interface between frontend & backend

* perf: modify perf-cnt for prefetchers

* Ftq: bypass 'commit state' to fix dequeue bug

* perf: uptimize perf-cnt in ctrlblock & ftq

* perf: fix compilation problem in ftq

* perf: remove duplicate perf-cnt

* perf: calcu extra walk cycle exceeding frontend flush bubble

* Revert "perf: calcu extra walk cycle exceeding frontend flush bubble"

This reverts commit 2c30e9896b6af93a34e2d8d78055d810ebd0ac70.

* perf: add perf-cnt for ifu

* perf: add perf-cnt for rs

* RS: optimize numExist signal

* RS: fix some typo

* perf: add QueuePerf util to monitor usage info of queues

* perf: remove some duprecate perfcnt

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RS: every rs has its own iqSize now (#710)

ReservationStation: fixed incorrect use of 'pc' (#709)

RS: add some signals' init value (#703)

RS & DTLB: fix bug of dtlb's hit perf counter (#689)

just record the tlb result(access and miss) of first issue by add
signal isFirstIssue (isFirstIssue = cntCountQueue(i) === 0.U)