rs: latch jump pc when deq is blocked (#1076)

This commit fixes a bug that causes pc to be wrong values when a jump is
blocked for issue and a new jump instruction enters reservation station.
When

rs: latch jump pc when deq is blocked (#1076)

This commit fixes a bug that causes pc to be wrong values when a jump is
blocked for issue and a new jump instruction enters reservation station.
When the jump for issue is blocked, we should latch its pc value because
the entry has been deallocated from rs (and pc no longer exists in the
pc mem).

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misc: code clean up (#1073)

* rename Roq to Rob

* remove trailing whitespaces

* remove unused parameters

rs: add pcMem to store pc for jalr instructions (#1064)

This commit adds storage for PC in JUMP reservation station. Jalr needs
four operands now, including rs1, pc, jalr_target and imm. Since Jump

rs: add pcMem to store pc for jalr instructions (#1064)

This commit adds storage for PC in JUMP reservation station. Jalr needs
four operands now, including rs1, pc, jalr_target and imm. Since Jump
currently stores two operands and imm, we have to allocate extra space
to store the one more extra operand for jalr.

It should be optimized later (possibly by reading jalr_target when
issuing the instruction).

This commit also adds regression check for PC usages. PC should not
enter decode stage.

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rs, fma: separate fadd and fmul issue (#1042)

This commit splits FMA instructions into FMUL and FADD for execution.

When the first two operands are ready, an FMA instruction can be issued
and th

rs, fma: separate fadd and fmul issue (#1042)

This commit splits FMA instructions into FMUL and FADD for execution.

When the first two operands are ready, an FMA instruction can be issued
and the intermediate result will be written back to RS after two cycles.
Since RS currently has DataArray to store the operands, we reuse it to
store the intermediate FMUL result.

When an FMA enters deq stage and leaves RS with only two operands, we
mark it as midState ready at this clock cycle T0.

If the instruction's third operand becomes ready at T0, it can be
selected at T1 and issued at T2, when FMUL is also finished. The
intermediate result will be sent to FADD instead of writing back to RS.
If the instruction's third operand becomes ready later, we have the data
in DataArray or at DataArray's write port. Thus, it's ok to set midState
ready at clock cycle T0.

The separation of FMA instructions will increase issue pressure since RS
needs to issue more times. However, it larges reduce FMA latency if many
FMA instructions are waiting for the third operand.

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backend,rs: load balance for issue selection (#1048)

This commit adds load balance strategy in issue selection logic for
reservation stations.

Previously we have a load balance option in ExuBloc

backend,rs: load balance for issue selection (#1048)

This commit adds load balance strategy in issue selection logic for
reservation stations.

Previously we have a load balance option in ExuBlock, but it cannot work
if the function units have feedbacks to RS. In this commit it is
removed.

This commit adds a victim index option for oldestFirst. For LOAD, the
first issue port has better performance and thus we set the victim index
to 0. For other function units, we use the last issue port.

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core: add timer counters for important stages (#1045)

This commit adds timer counters for some important pipeline stages,
including rename, dispatch, dispatch2, select, issue, execute, commit.
We

core: add timer counters for important stages (#1045)

This commit adds timer counters for some important pipeline stages,
including rename, dispatch, dispatch2, select, issue, execute, commit.
We add performance counters for different types of instructions to see
the latency in different pipeline stages.

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backend,rs: add counters for critical wakeup sources (#1027)

This commit adds critical_wakeup_*_* counters to indicate which function
units wake up the instructions in RS. Previously we have wait_f

backend,rs: add counters for critical wakeup sources (#1027)

This commit adds critical_wakeup_*_* counters to indicate which function
units wake up the instructions in RS. Previously we have wait_for_src_*
counters but they cannot represent where the critical operand (the last
waiting operand) comes from.

We need these counters to optimize fast wakeup logic. If some
instructions critically depend on some other instructions, we can think
of how we can optimize the wakeup process.

Furthermore, this commit also adds a specific counter for FMAs that
wakeup other FMAs' third operand. This helps us to decide which strategy
is used for FMA fast issue.

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backend,rs: move select logic to stage 0 (#1023)

This commit moves issue select logic in reservation stations to stage 0
from stage 1. It helps timing of stage 1, which load-to-load requires.

No

backend,rs: move select logic to stage 0 (#1023)

This commit moves issue select logic in reservation stations to stage 0
from stage 1. It helps timing of stage 1, which load-to-load requires.

Now, reservation stations have the following stages:

* S0: enqueue and wakeup, select. Selection results are RegNext-ed.
* S1: data/uop read and data bypass. Bypassed results are RegNext-ed.
* S2: issue instructions to function units.

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rs,status: simplify logic to optimize timing (#1020)

This commit simplifies status logic in reservations stations. Module
StatusArray is mostly rewritten.

The following optimizations are applied

rs,status: simplify logic to optimize timing (#1020)

This commit simplifies status logic in reservations stations. Module
StatusArray is mostly rewritten.

The following optimizations are applied:

* Wakeup now has higher priority than enqueue. This reduces the length
of the critical path of ALU back-to-back wakeup.

* Don't compare fpWen/rfWen if the reservation station does not have
float/int operands.

* Ignore status.valid or redirect for srcState update. For data capture,
these are necessary and not changed.

* Remove blocked and scheduled conditions in issue logic when the
reservation station does not have loadWait bit and feedback.

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backend, rs: parallelize selection and data read (#1018)

This commit changes how uop and data are read in reservation stations.
It helps the issue timing.

Previously, we access payload array and

backend, rs: parallelize selection and data read (#1018)

This commit changes how uop and data are read in reservation stations.
It helps the issue timing.

Previously, we access payload array and data array after we decide the
instructions that we want to issue. This method makes issue selection
and array access serialized and brings critial path.

In this commit, we add one more read port to payload array and data
array. This extra read port is for the oldest instruction. We decide
whether to issue the oldest instruction and read uop/data
simultaneously. This change reduces the critical path to each selection
logic + read + Mux (previously it's selection + arbitration + read).

Variable oldestOverride indicates whether we choose the oldest ready
instruction instead of the normal selection. An oldestFirst option is
added to RSParams to parameterize whether we need the age logic. By
default, it is set to true unless the RS is for ALU. If the timing for
aged ALU rs meets, we will enable it later.

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Merge branch 'master' into vaddr-fwd

rs,mem: support fast load-to-load wakeup and issue (#984)

This PR adds support for fast load-to-load wakeup and issue. In load-to-load fast wakeup and issue, load-to-load latency is reduced to 2 cyc

rs,mem: support fast load-to-load wakeup and issue (#984)

This PR adds support for fast load-to-load wakeup and issue. In load-to-load fast wakeup and issue, load-to-load latency is reduced to 2 cycles.

Now a load instruction can wakeup another load instruction at LOAD stage 1. When the producer load instruction arrives at stage 2, the consumer load instruction is issued to load stage 0 and using data from the producer to generate load address.

In reservation station, load can be dequeued from staged 1 when stage 2 does not have a valid instruction. If the fast load is not accepted, from the next cycle on, the load will dequeue as normal.

Timing in reservation station (for imm read) and load unit (for writeback data selection) to be optimized later.

* backend,rs: issue load one cycle earlier when possible

This commit adds support for issuing load instructions one cycle
earlier if the load instruction is wakeup by another load. An extra
2-bit UInt is added to IO.

* mem: add load to load addr fastpath framework

* mem: enable load to load forward

* mem: add load-load forward counter

Co-authored-by: William Wang <[email protected]>

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Merge remote-tracking branch 'origin/master' into vaddr-fwd

rs,bypass: add left and right bypass strategy (#971)

* rs,bypass: remove optBuf for valid bits

* rs,bypass: add left and right bypass strategy

This commit adds another bypass network implement

rs,bypass: add left and right bypass strategy (#971)

* rs,bypass: remove optBuf for valid bits

* rs,bypass: add left and right bypass strategy

This commit adds another bypass network implementation to optimize timing of the first stage of function units.

In BypassNetworkLeft, we bypass data at the same cycle that function units write data back. This increases the length of the critical path of the last stage of function units but reduces the length of the critical path of the first stage of function units. Some function units that require a shorter stage zero, like LOAD, may use BypassNetworkLeft.

In this commit, we set all bypass networks to the left style, but we will make it configurable depending on different function units in the future.

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rs,age: optimize timing for output (#970)

This commit changes how io.out is computed for age detector. We use a
register to keep track of the position of the oldest instruction. Since
the updating i

rs,age: optimize timing for output (#970)

This commit changes how io.out is computed for age detector. We use a
register to keep track of the position of the oldest instruction. Since
the updating information has better timing than issue, this could
optimize the timing of issue logic.

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rs,age: use less registers for age matrix (#964)

This commit reduces register usage in age detector via using the
upper matrix only. Since the age matrix is symmetric, age(i)(j)
equals !age(j)(i).

rs,age: use less registers for age matrix (#964)

This commit reduces register usage in age detector via using the
upper matrix only. Since the age matrix is symmetric, age(i)(j)
equals !age(j)(i). Besides, age(i)(i) is the same as valid(i).
Thus, we also remove validVec in this commit.

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backend,fu: allow early arbitration via fastUopOut (#962)

This commit adds a fastUopOut option to function units. This allows the
function units to give valid and uop one cycle before its output da

backend,fu: allow early arbitration via fastUopOut (#962)

This commit adds a fastUopOut option to function units. This allows the
function units to give valid and uop one cycle before its output data is
ready. FastUopOut lets writeback arbitration happen one cycle before
data is ready and helps optimize the timing.

Since some function units are not ready for this new feature, this
commit adds a fastImplemented option to allow function units to have
fastUopOut but the data is still at the same cycle as uop. This option
will delay the data for one cycle and may cause performance degradation.
FastImplemented should be true after function units support fastUopOut.

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l2, core: add more performance counters (#942)

* Refactor print control transform

* Adda tilelink bus pmu

* Add performance counters for dispatch, issue, execute stages

* Add more counters

l2, core: add more performance counters (#942)

* Refactor print control transform

* Adda tilelink bus pmu

* Add performance counters for dispatch, issue, execute stages

* Add more counters in bus pmu

* Insert BusPMU between L3 and L2

* add some TMA perfcnt



Co-authored-by: LinJiawei <[email protected]>
Co-authored-by: William Wang <[email protected]>
Co-authored-by: wangkaifan <[email protected]>

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backend, rs: add an age matrix to find the oldest instruction (#937)

* backend, rs: add an age matrix to find the oldest instruction

This commit adds an age matrix to reservation station to find

backend, rs: add an age matrix to find the oldest instruction (#937)

* backend, rs: add an age matrix to find the oldest instruction

This commit adds an age matrix to reservation station to find
the oldest instruction. This enables the RS to schedule the oldest
instruction first.

This commit also adda performance counter for oldest inst

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backend, rs: add a maximum dequeue width (default 2) (#935)

This commit limits dequeue width of every RS to 2 for better timing.

backend: separate store address and data (#921)

This commit separates store address and store data in backend, including both reservation stations and function units. This commit also changes how st

backend: separate store address and data (#921)

This commit separates store address and store data in backend, including both reservation stations and function units. This commit also changes how stIssuePtr is updated. stIssuePtr should only be updated when both store data and address issue.

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mem: loadpipe will not miss if fullForward succeed

New option `EnableFastForward` is added to config list.
EnableFastForward will reduce L1D$ miss but make timing worse.

* `forwardMaskFast` is gene

mem: loadpipe will not miss if fullForward succeed

New option `EnableFastForward` is added to config list.
EnableFastForward will reduce L1D$ miss but make timing worse.

* `forwardMaskFast` is generated at load_s1, it is used to generate
fastUop for fast wakeup
* `forwardMask` is generated at load_s2, it will be used to check if
forward result is correct

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backend: add ExuBlock to wrap execution units and RS (#903)

Backend --> ExuBlock --> FuBlock --> Exu --> Function Units
--> --> Scheduler --> RS

scheduler: allow multiple-dequeue RS for load and store (#895)

This commit adds support for multiple enqueue for load and store RS.
Also update the parameters in XSCore to avoid explicitly setting

scheduler: allow multiple-dequeue RS for load and store (#895)

This commit adds support for multiple enqueue for load and store RS.
Also update the parameters in XSCore to avoid explicitly setting wakeup ports.

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backend,rs: compare sqPtr when enqueue (#892)

Compare SqPtr when an instruction with wait bit enqueuing. This should have minor
performance improvements. Also add some performance counters.