issue - OpenGrok history log for /XiangShan/src/main/scala/xiangshan/backend/issue

Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
a01a12bb	20-Dec-2023	Haojin Tang <[email protected]>	IssueQueue: connect missing wakeup copy signals /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala IssueQueue.scala
fc45ed13	16-Feb-2024	Xuan Hu <[email protected]>	Scheduler: fix loadWakeUp for load2load Scheduler.scala
596af5d2	20-Dec-2023	Haojin Tang <[email protected]>	Scheduler: implement wakeup from LoadUnit /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala IssueQueue.scala SchdBlockParams.scala Scheduler.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
0dfdb52a	20-Dec-2023	zhanglyGit <[email protected]>	Backend: fix performance bug of ld wakeup EnqEntry.scala EntryBundles.scala OthersEntry.scala
27811ea4	15-Feb-2024	Xuan Hu <[email protected]>	Backend: limit num of enq no more than 2 /XiangShan/src/main/scala/xiangshan/Parameters.scala Entries.scala
aa2bcc31	19-Dec-2023	zhanglyGit <[email protected]>	Backend: refactor Entries /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala EnqEntry.scala Entries.scala EntryBundles.scala IssueQueue.scala OthersEntry.scala Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala
5f4ac341	18-Dec-2023	xiaofeibao-xjtu <[email protected]>	wakeup: remove flush between iq and wakeup queue /XiangShan/src/main/scala/utils/PipeWithFlush.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala MultiWakeupQueue.scala
8321ef33	13-Dec-2023	sinsanction <[email protected]>	Entries: optimize transfer policy /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala EnqPolicy.scala Entries.scala OthersEntry.scala
0721d1aa	24-Jan-2024	Xuan Hu <[email protected]>	backend: add desired name for IssueQueue/Entries Module Entries.scala IssueBlockParams.scala IssueQueue.scala
2aaa83c0	08-Dec-2023	xiaofeibao-xjtu <[email protected]>	backend: WBArbiter support two out at same time, fast wakeup remove valid /XiangShan/src/main/scala/utils/PipeWithFlush.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/RFWBConflictChecker.scala EnqEntry.scala MultiWakeupQueue.scala OthersEntry.scala
4c5a0d77	06-Dec-2023	xiaofeibao-xjtu <[email protected]>	WakeupQueue: Copy all bits /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala IssueBlockParams.scala IssueQueue.scala SchdBlockParams.scala Scheduler.scala
543f3ac7	06-Dec-2023	sinsanction <[email protected]>	IssueQueue: use Vec[Bool] to store FuType for less reg & wire usage EnqEntry.scala Entries.scala IssueQueue.scala OthersEntry.scala
ec1fea84	05-Dec-2023	zhanglyGit <[email protected]>	Backend: optimize wakeupQueue timing /XiangShan/src/main/scala/utils/PipeWithFlush.scala IssueQueue.scala MultiWakeupQueue.scala
60912d84	04-Dec-2023	xiaofeibao-xjtu <[email protected]>	IQ: remove useless logic Wen and pdest=0 /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala IssueQueue.scala Scheduler.scala
96aaae3f	04-Dec-2023	sinsanction <[email protected]>	IssueQueue: remove unused deq psrc check /XiangShan/src/main/scala/xiangshan/Parameters.scala IssueQueue.scala
0c7ebb58	04-Dec-2023	xiaofeibao-xjtu <[email protected]>	WakeupQueue: pdest copy /XiangShan/src/main/scala/utils/PipeWithFlush.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WakeUpConfig.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala IssueBlockParams.scala IssueQueue.scala MultiWakeupQueue.scala SchdBlockParams.scala Scheduler.scala /XiangShan/src/test/scala/xiangshan/backend/issue/MultiWakeupQueueMain.scala /XiangShan/src/test/scala/xiangshan/utils/GenPipeWithFlush.scala
d20f567f	01-Dec-2023	zhanglyGit <[email protected]>	Backend: optimize some implement EnqEntry.scala OthersEntry.scala
79b2c95b	30-Nov-2023	zhanglyGit <[email protected]>	Backend: fix lat>0 cancel error /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala EnqEntry.scala IssueQueue.scala OthersEntry.scala
1f35da39	29-Nov-2023	xiaofeibao-xjtu <[email protected]>	backend: change vfSchdParams, add PipelineConnect name /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala EnqEntry.scala Entries.scala OthersEntry.scala
acf41503	29-Nov-2023	sinsanction <[email protected]>	EnqEntry, OthersEntry: reduce srcWakeUpL1ExuOH width EnqEntry.scala IssueBlockParams.scala OthersEntry.scala
291e39d9	29-Nov-2023	sinsanction <[email protected]>	AgeDetector: reduce reg usage AgeDetector.scala NewAgeDetector.scala
f39a61a1	29-Nov-2023	zhanglyGit <[email protected]>	Backend: remove per IQ's wbWakeup /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala IssueBlockParams.scala SchdBlockParams.scala Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
44d24a97	23-Jan-2024	Xuan Hu <[email protected]>	EnqEntry: fix unconnected port EnqEntry.scala
7cbafe1a	27-Nov-2023	zhanglyGit <[email protected]>	Backend: fix srcCancel and ExuOHOut timing EnqEntry.scala OthersEntry.scala
13551487	23-Nov-2023	zhanglyGit <[email protected]>	Backend: BusyTable supports load fastwakeup /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala Dispatch2Iq.scala EnqEntry.scala IssueQueue.scala Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
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