History log of /XiangShan/src/main/scala/xiangshan/backend/issue/ (Results 151 – 175 of 794)
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5d750ac219-Jan-2024 Zhaoyang You <[email protected]>

VLUopQueue & Dispatch2Iq: fix recover entry when redirect & fix load deq ports selection (#2659)

* VLUopQueue: fix recover entry when redirect

* Dispatch2Iq: fix load deq ports selection

Co-au

VLUopQueue & Dispatch2Iq: fix recover entry when redirect & fix load deq ports selection (#2659)

* VLUopQueue: fix recover entry when redirect

* Dispatch2Iq: fix load deq ports selection

Co-authored-by: Haojin Tang <[email protected]>

---------

Co-authored-by: Haojin Tang <[email protected]>

show more ...


Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VLUopQueue.scala
99944b7927-Feb-2024 sinsanction <[email protected]>

IssueQueue, Entries: refactor vector mem Entries


EnqEntry.scala
Entries.scala
EntryBundles.scala
IssueBlockParams.scala
IssueQueue.scala
OthersEntry.scala
c758aa7f27-Feb-2024 sinsanction <[email protected]>

IssueQueue: remove vector mem signals from scalar mem IQ


IssueQueue.scala
b43488b927-Feb-2024 sinsanction <[email protected]>

Entries: add some comments about transfer policy


Entries.scala
d337221027-Feb-2024 zhanglyGit <[email protected]>

MemResp: fix bug --> hyu still needs fastResp


/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala
Entries.scala
IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
6462eb1c26-Feb-2024 zhanglyGit <[email protected]>

Backend: refactor LDU resp


/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
Entries.scala
IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
5c1f97cc26-Feb-2024 sinsanction <[email protected]>

IssueQueue: disable the deq port of FakeHysta


/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
IssueQueue.scala
80c686d523-Feb-2024 zhanglyGit <[email protected]>

IssueQueue: use getLdExuIdx to generate loadDependency


/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
9dfdaed224-Jan-2024 xiaofeibao-xjtu <[email protected]>

Dispatch2Iq: balance optimize


Dispatch2Iq.scala
190cbcf322-Jan-2024 xiaofeibao-xjtu <[email protected]>

Dispatch2Iq: fix bug of brh1 select


/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataSource.scala
Dispatch2Iq.scala
c4fc226a16-Jan-2024 xiaofeibao-xjtu <[email protected]>

backend: add DataSource anotherReg


/XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataSource.scala
IssueQueue.scala
53bf098f16-Jan-2024 xiaofeibao-xjtu <[email protected]>

IssueQueue: read int preg which psrc is 0 without sending a read request


/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataSource.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RFReadArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RFWBConflictChecker.scala
EnqEntry.scala
EntryBundles.scala
IssueQueue.scala
19c9a26f11-Jan-2024 xiaofeibao-xjtu <[email protected]>

dispatch2iq: fix bug of uop1 select


Dispatch2Iq.scala
6fa1007b10-Jan-2024 xiaofeibao-xjtu <[email protected]>

wakeup: add mul wakeup


/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
IssueQueue.scala
c1e1966604-Jan-2024 xiaofeibao-xjtu <[email protected]>

backend: implement uncertain latency exeUnit WbArbiter


/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RFReadArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/BranchUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/JumpUnit.scala
Dispatch2Iq.scala
Scheduler.scala
ff3fcdf115-Dec-2023 xiaofeibao-xjtu <[email protected]>

Dispatch: split int dispatch to two regions


/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RFReadArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala
Dispatch2Iq.scala
IssueQueue.scala
Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
6310147803-Jan-2024 Haojin Tang <[email protected]>

LoadUnit: remove load writeback wakeup


/XiangShan/src/main/scala/xiangshan/backend/datapath/RFReadArbiter.scala
IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
a6938b1702-Jan-2024 sinsanction <[email protected]>

Entries: add some perf counter


Entries.scala
EntryBundles.scala
f08a822f27-Dec-2023 zhanglyGit <[email protected]>

Backend: optimize resp signal


/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
EntryBundles.scala
FuBusyTableWrite.scala
IssueQueue.scala
eea4a3ca27-Dec-2023 zhanglyGit <[email protected]>

IssueQueue: fix loadDependency bug


EnqEntry.scala
Entries.scala
EntryBundles.scala
IssueQueue.scala
2860707426-Dec-2023 sinsanction <[email protected]>

IssueQueue: add Simple to Complex transfer policy & support all Complex/Simple entry config


/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
EnqEntry.scala
Entries.scala
EntryBundles.scala
IssueBlockParams.scala
IssueQueue.scala
OthersEntry.scala
df26db8a21-Dec-2023 sinsanction <[email protected]>

IssueQueue: support Complex/Simple Entry


EnqEntry.scala
Entries.scala
EntryBundles.scala
OthersEntry.scala
397c0f3321-Dec-2023 sinsanction <[email protected]>

EnqEntry, OthersEntry: both use entryUpdate for easier transfer later


EnqEntry.scala
Entries.scala
EntryBundles.scala
OthersEntry.scala
3d81019f21-Dec-2023 zhanglyGit <[email protected]>

IssueQueue: optimize loadDependency timing


Entries.scala
IssueQueue.scala
a4d38a6320-Dec-2023 zhanglyGit <[email protected]>

IssueQueue: optimize ldcancel timing


Entries.scala
EntryBundles.scala

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