issue - OpenGrok history log for /XiangShan/src/main/scala/xiangshan/backend/issue

Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
08047a41	12-Apr-2024	Anzooooo <[email protected]>	VLSU: fix numLsElem width and also make code more formal /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
b0186a50	06-Apr-2024	weiding liu <[email protected]>	Backend, IQ: suport vector load/store issued out-of-order /XiangShan/difftest /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala EntryBundles.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
9ae95eda	02-Apr-2024	Anzooooo <[email protected]>	Difftest: add new VLSU difftest support /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
a37532b3	06-Apr-2024	Anzooooo <[email protected]>	Dispatch2Iq: fix bug caused by incorrect naming order Dispatch2Iq.scala
32977e5d	02-Apr-2024	Anzooooo <[email protected]>	Dispatch2Iq, package: make the encoding and decoding more standardized /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala /XiangShan/src/main/scala/xiangshan/package.scala
8f3cbbcf	05-Apr-2024	Xuan Hu <[email protected]>	Backend: add vector load border response * The border response will be set success when the vector load uop pass to MemBlock like load Entries.scala
711fe6a2	03-Apr-2024	weiding liu <[email protected]>	Dispatch2Iq: fix bug of vector load/store & amo dispatch this commit fix the situation that enqLsq_0 not allocate lsq entries, but enqLsq_1 allocate lsq entries. Dispatch2Iq.scala
7e471bf8	03-Apr-2024	Xuan Hu <[email protected]>	Backend: add vector load border response * The border response will be set success when the vector load uop pass to MemBlock like load /XiangShan/src/main/scala/xiangshan/backend/Backend.scala Entries.scala IssueQueue.scala Scheduler.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
64c8c03b	03-Apr-2024	good-circle <[email protected]>	Dispatch2Iq: fix bug of allocate lsq entry and enq logic /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
fd490615	02-Apr-2024	weiding liu <[email protected]>	Backend,MemBlock: add uopIdx for vector load/store feedback /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala IssueQueue.scala Scheduler.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
f7890d3c	01-Apr-2024	Xuan Hu <[email protected]>	Backend: support feedback for vector load/store /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala Entries.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
ebb914e7	01-Apr-2024	weiding liu <[email protected]>	VLSU: add framework of vector store feedback /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala Scheduler.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
b9b5052c	30-Mar-2024	weiding liu <[email protected]>	Dispatch2Iq,VLSU: fix uop of flowNum /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
3ea758f9	31-Mar-2024	Anzo <[email protected]>	VLSU: fix allocated LSQ entries (#2829) /XiangShan/src/main/scala/xiangshan/Parameters.scala Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
1503b106	30-Mar-2024	Anzo <[email protected]>	rv64v: fix calculation of 'numLsElem' (#2823) Dispatch2Iq.scala
6dbb4e08	28-Mar-2024	Xuan Hu <[email protected]>	Backend: support vector load&store better * Todo: add more IQs for vector load&store * Todo: make vector memory inst issue out of order * Todo: fix bugs /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala Dispatch2Iq.scala EntryBundles.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala /XiangShan/src/main/scala/xiangshan/package.scala
f3a9fb05	27-Mar-2024	Anzo <[email protected]>	rv64v: add support for vlsu continuous 'uop' (#2816) add LSQ backpressure logic and 'uop' continuous application LSQ entries logic /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/utils/ClockGate.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/RFWBConflictChecker.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntFPToVec.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecNonPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala Dispatch2Iq.scala Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/yunsuan
ec49b127	19-Apr-2024	sinsanction <[email protected]>	Backend: reduce the width of LoadDependency to 2 bits /XiangShan/.github/workflows/nightly.yml /XiangShan/difftest /XiangShan/huancun /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/utils/PipeWithFlush.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WakeUpConfig.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/ByteMaskTailGen.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala Dispatch2Iq.scala EnqEntry.scala Entries.scala EntryBundles.scala IssueBlockParams.scala IssueQueue.scala MultiWakeupQueue.scala SchdBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/test/scala/xiangshan/backend/fu/vector/ByteMaskTailGenTest.scala /XiangShan/utility
7e4f0b19	17-Apr-2024	Ziyue-Zhang <[email protected]>	rv64v: fix the logic of writing vtype for vsetvl instruction (#2875) /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala IssueBlockParams.scala SchdBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
1b86a038	16-Apr-2024	Haojin Tang <[email protected]>	Dispatch2Iq: fix store dispatch policy Dispatch2Iq.scala
09d562ee	15-Apr-2024	sinsanction <[email protected]>	EnqEntry: fix condition of bypass2 in vf -> mem /XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala EnqEntry.scala /XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
2734c4a6	15-Apr-2024	xiao feibao <[email protected]>	Entry: mem wakeup by vf use bypass2 EnqEntry.scala EntryBundles.scala
c4cabf18	12-Apr-2024	sinsanction <[email protected]>	Entry: refactor dataSource update /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala EnqEntry.scala EntryBundles.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
a75d561c	11-Apr-2024	sinsanction <[email protected]>	Entry: fix dataSource update of mem IQ /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/RFWBConflictChecker.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala EntryBundles.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
de111a36	07-Apr-2024	sinsanction <[email protected]>	IssueQueue: add vf <-> mem fast wake up /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala EnqEntry.scala EntryBundles.scala IssueBlockParams.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
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