6683fc49 | 25-Apr-2025 |
Zhaoyang You <[email protected]> |
fix(csr): filter out Read-Only CSR in regOut (#4412) |
1191982f | 24-Apr-2025 |
Zhaoyang You <[email protected]> |
fix(intr,difftest): add interrupt delegate (#4516) |
6e51c65d | 16-Apr-2025 |
sinceforYy <[email protected]> |
fix(vstopi): fix vstopi result selection
* AIA Spec: * Ties in nominal priority are broken as usual by the default priority * order from Table 8, unless hvictl fields VTI = 1 and IID ≠ 9 * (last ite
fix(vstopi): fix vstopi result selection
* AIA Spec: * Ties in nominal priority are broken as usual by the default priority * order from Table 8, unless hvictl fields VTI = 1 and IID ≠ 9 * (last item in the candidate list above), in which case * default priority order is determined solely by hvictl.DPR.
* If bit IPRIOM (IPRIO Mode) of hvictl is zero, IPRIO in vstopi is 1; * else, if the priority number for the highest-priority candidate * is within the range 1 to 255, IPRIO is that value; else, IPRIO * is set to either 0 or 255 in the manner documented for stopi * in Section 5.4.2.
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ece71978 | 15-Apr-2025 |
sinceforYy <[email protected]> |
fix(xtopi): fix m/stopi.IRPIO generation conditions
* If all bytes of the supervisor-level iprio array are read-only zeros, * a simplified implementation of field IPRIO is allowed in which * its val
fix(xtopi): fix m/stopi.IRPIO generation conditions
* If all bytes of the supervisor-level iprio array are read-only zeros, * a simplified implementation of field IPRIO is allowed in which * its value is always 1 whenever stopi is not zero. * * We are configurable and do not need to simplify the implementation.
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f9ed852f | 22-Apr-2025 |
NewPaulWalker <[email protected]> |
fix(xiselect): set the minimum range for xiselect (#4594)
The miselect register implements at least enough bits to support all implemented miselect values. The siselect register will support the val
fix(xiselect): set the minimum range for xiselect (#4594)
The miselect register implements at least enough bits to support all implemented miselect values. The siselect register will support the value range 0..0xFFF at a minimum. The vsiselect register will support the value range 0..0xFFF at a minimum.
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bcc5f81f | 18-Apr-2025 |
Zhaoyang You <[email protected]> |
fix(csr): fix trap handle bundle format (#4579) |
011d262c | 15-Apr-2025 |
Zhaoyang You <[email protected]> |
feat(PMA, CSR): support PMA CSR configurable (#4233) |
3933ec0c | 15-Apr-2025 |
Zhaoyang You <[email protected]> |
fix(vstopi): remove SEI from Candidate 4 (#4533)
* if hvictl.VTI = 0: * the highest-priority pending-and-enabled major interrupt indicated * by vsip and vsie other than a supervisor external interru
fix(vstopi): remove SEI from Candidate 4 (#4533)
* if hvictl.VTI = 0: * the highest-priority pending-and-enabled major interrupt indicated * by vsip and vsie other than a supervisor external interrupt(code 9), * using the priority numbers assigned by hviprio1 and hviprio2. * * A hypervisor can choose to employ registers hviprio1 and hviprio2 * when emulating the (virtual) supervisor-level iprio array accessed * indirectly through siselect and sireg (really vsiselect and vsireg) * for a virtual hart. For interrupts not in the subset supported by * hviprio1 and hviprio2, the priority number bytes in the emulated * iprio array can be read-only zeros.
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c38ad5d1 | 15-Apr-2025 |
Guanghui Cheng <[email protected]> |
fix(CSR): remove useless logic of `mIRVec` (#4553) |
6127035c | 09-Apr-2025 |
Zhaoyang You <[email protected]> |
fix(difftest): fix sync aia event valid (#4517) |
7768a97d | 08-Apr-2025 |
Tang Haojin <[email protected]> |
fix(CSR): use GEILEN from IMSICParams (#4520) |
8cfc24b2 | 07-Apr-2025 |
Tang Haojin <[email protected]> |
feat(AIA): integrate ChiselAIA again (#4509) |
69e67bbf | 22-Mar-2025 |
Tang Haojin <[email protected]> |
fix(difftest, CSR): sync non-reg interrupt pending right after reset (#4449) |
529b1cfd | 17-Mar-2025 |
Tang Haojin <[email protected]> |
Revert "feat(AIA): integrate ChiselAIA (#4378)" (#4429)
This reverts commit 7fbc1cb42a2c96ef89a1dfd0f5f885ccada40c26. |
a9115dab | 14-Mar-2025 |
sinceforYy <[email protected]> |
fix(csr, difftest): do not update difftest framework on reset |
8893eb2c | 12-Mar-2025 |
Zhaoyang You <[email protected]> |
fix(csr): CSRR instruction read xireg inOrder (#4393)
* AIA registers are designed to be access asynchronously, so newCSR will wait for response. Therefore, CSRR instruction read mireg/sireg/vsireg
fix(csr): CSRR instruction read xireg inOrder (#4393)
* AIA registers are designed to be access asynchronously, so newCSR will wait for response. Therefore, CSRR instruction read mireg/sireg/vsireg inOrder.
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7fbc1cb4 | 08-Mar-2025 |
Tang Haojin <[email protected]> |
feat(AIA): integrate ChiselAIA (#4378) |
ef82825f | 07-Mar-2025 |
junxiong-ji <[email protected]> |
fix(CSR): add VTYPE to in-order read CSRs (#4354)
Since CSR VTYPE is not renamed (VL is renamed), the instruction CSRR with VTYPE cannot be executed out-of-order. |
a67fd0f5 | 28-Feb-2025 |
Guanghui Cheng <[email protected]> |
fix(PFEvent): use `CSRModule` for distribute_csr in PFEvent (#4321) |
eca6983f | 26-Feb-2025 |
Zehao Liu <[email protected]> |
fix(dbltrp): set sdt to 0 when exe sret to VU (#4313) |
ceaa4109 | 24-Feb-2025 |
junxiong-ji <[email protected]> |
style(csr): fix typo in CSR (#4310) |
21e8685b | 21-Feb-2025 |
Zhaoyang You <[email protected]> |
fix(xtval): fix xtval when raise intr (#4307) |
8882eb68 | 21-Feb-2025 |
Xin Tian <[email protected]> |
feat(bitmap/memenc): support memory isolation by bitmap checking and memory encrpty used SM4-XTS (#3980)
- Add bitmap module in MMU for memory isolation - Add memory encryption module based on AXI p
feat(bitmap/memenc): support memory isolation by bitmap checking and memory encrpty used SM4-XTS (#3980)
- Add bitmap module in MMU for memory isolation - Add memory encryption module based on AXI protoco - Can don't using these modules by setting the option `HasMEMencryption` & `HasBitmapCheck` to false
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075d4937 | 30-Dec-2024 |
junxiong-ji <[email protected]> |
feat(CSR): allow most CSRR can be out-of-order issued and executed
* Add some comment on rdata in NewCSR. * Allow CSRR not to block backward instruction. * Here is **Inorder** CSRR list, * fflags,
feat(CSR): allow most CSRR can be out-of-order issued and executed
* Add some comment on rdata in NewCSR. * Allow CSRR not to block backward instruction. * Here is **Inorder** CSRR list, * fflags, fcsr, * vxsat, vcsr, vstart, * mstatus, sstatus, hstatus, vsstatus, mnstatus, * dcsr. * The reason for Inorder CSRR executed is that these CSR will be changed by Use-Level instruction without any fence, and executing OoO would get wrong result. * Since there must be FENCE before reading any PMC CSRs, there is no need to let reading PMC CSRs inorder.
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3c808de0 | 17-Feb-2025 |
Anzo <[email protected]> |
fix(LSU): fix cbo instr exceptions and implementation (#4262)
1. typo.
2. `cbo` instr not produce misaligned exception.
3. `cbo zero` instr need flush `sbuffer`.
4. `cbo zero` sets mask correctly
fix(LSU): fix cbo instr exceptions and implementation (#4262)
1. typo.
2. `cbo` instr not produce misaligned exception.
3. `cbo zero` instr need flush `sbuffer`.
4. `cbo zero` sets mask correctly
5. Adding RAW checks to `cbo zero`.
6. Adding trigger(Debug Mode) checks to `cbo zero`.
7. Fixed several issues with the CBO instruction in NEMU.
----
In order not to create ambiguity with `io.mmioStout`, a new port of
`StoreQueue` is introduced for writeback `cbo zero` after flush sbuffer.
arbitration is performed in `MemBlock`, and currently, `cbo zero` has
higher priority by default.
`cbo zero` should not be writteback at the same time as `mmio`.
---
A check on `CacheLine` has been added to `RAWQueue` to ensure memory
consistency when executing `cbo zero`.
See this issues:https://github.com/OpenXiangShan/XiangShan/issues/4240
for specific issues.
---
The `cbo` instruction requires a trigger check.
---------
Co-authored-by: zhanglinjuan <[email protected]>
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