decode - OpenGrok history log for /XiangShan/src/main/scala/xiangshan/backend/decode

Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
cafb3558	11-Jul-2020	LinJiawei <[email protected]>	Refactor exu /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile /XiangShan/build.sbt /XiangShan/build.sc /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala Decoder.scala isa/RVI.scala isa/RVM.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/DivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/LsExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fmac.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fmisc.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/I2f.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xiangshan/utils/PriorityMuxDefault.scala /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/AluTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/LsuTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/MduTest.scala /XiangShan/src/test/scala/xiangshan/testutils/TestCaseGenerator.scala
76aed3fc	09-Jul-2020	LinJiawei <[email protected]>	XSTrap: add custom trap inst to make difftest happy /XiangShan/Makefile /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala DecodeHelper.scala Decoder.scala XSTrap.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Lsu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Mul.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeIFU.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/monitor.cpp /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/exu/MduTest.scala /XiangShan/src/test/scala/xiangshan/testutils/TestCaseGenerator.scala
bfa4b2b4	04-Jul-2020	LinJiawei <[email protected]>	Cmp brTag /XiangShan/build.sc /XiangShan/debug/Makefile /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Bru.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/utils/LogUtils.scala /XiangShan/src/test/scala/xiangshan/backend/exu/AluTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/LsuTest.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala /XiangShan/src/test/scala/xiangshan/testutils/PartialDecoupledDriver.scala /XiangShan/src/test/scala/xiangshan/testutils/TestCaseGenerator.scala
a66fc743	04-Jul-2020	LinJiawei <[email protected]>	DecodeBuffer: adjust log fmt DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala
ebfa1e8e	04-Jul-2020	LinJiawei <[email protected]>	Add log info /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Lsu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeIFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xiangshan/utils/MIMOQueue.scala /XiangShan/src/test/csrc/emu.h
5386f9e2	02-Jul-2020	LinJiawei <[email protected]>	Decode: set DecodeWidth to 6 /XiangShan/.gitignore /XiangShan/build.sc /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Bru.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Lsu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeIFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/scala/top/XSSim.scala
926e418c	29-Jun-2020	LinJiawei <[email protected]>	Decode Buffer: set valid to 0 when redirect DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala
36fe39b1	28-Jun-2020	William Wang <[email protected]>	decode: care about DONTCARE /XiangShan/Makefile /XiangShan/debug/Makefile /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Bru.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Lsu.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/utils/LogUtils.scala /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/log.cpp /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/stale_outputs_checked
1dccb266	26-Jun-2020	Yinan Xu <[email protected]>	debug: add debug log /XiangShan/Makefile /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala DecodeBuffer.scala DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/utils/LogUtils.scala /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/scala/top/XSSim.scala
e201dec9	25-Jun-2020	YikeZhou <[email protected]>	backend/decode/Decoder.scala: modify `isBr` to include jal and jalr Decoder.scala
e4104fa4	25-Jun-2020	YikeZhou <[email protected]>	backend/decode/Decoder.scala: add isBr check temporarily. Decoder.scala
ead0fcff	25-Jun-2020	YikeZhou <[email protected]>	backend/decode/DecodeStage.scala: add XSDebug info output messages when detecting br instr or brq full or decbuf full /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/utils/LogUtils.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/scala/top/XSSim.scala
973d04d8	25-Jun-2020	YikeZhou <[email protected]>	backend/decode/DecodeStage.scala: correct io.toBrq(i).valid signal DecodeStage.scala
1ca83654	24-Jun-2020	YikeZhou <[email protected]>	Merge branch 'master' into decoder-dev /XiangShan/.gitignore /XiangShan/Makefile /XiangShan/build.sc /XiangShan/src/main/scala/top/TopMain.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala DecodeBuffer.scala DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Lsu.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/utils/MIMOQueue.scala /XiangShan/src/test/scala/top/XSSim.scala
585901de	24-Jun-2020	YikeZhou <[email protected]>	backend/decode/Decoder.scala: add isXSTrap signal Decoder.scala
ad899085	24-Jun-2020	YikeZhou <[email protected]>	backend/decode/DecodeStage.scala: implement handshake control DecodeStage.scala
c050f1cc	24-Jun-2020	YikeZhou <[email protected]>	backend/decode/Decoder.scala, DecoderHelper.scala: add a decoder supporting I & M instruction set DecodeHelper.scala Decoder.scala
addeb238	24-Jun-2020	YikeZhou <[email protected]>	backend/decode/isa/*: add ISA bitpats and decode tables. backend/package.scala: add FuOpType constants. /XiangShan/.github/workflows/core_ci.yml /XiangShan/Makefile /XiangShan/fpga/board/axu3cg/constr/hdmi.xdc /XiangShan/fpga/board/axu3cg/rtl/system_top.v /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala isa/Privileged.scala isa/RVA.scala isa/RVC.scala isa/RVD.scala isa/RVF.scala isa/RVI.scala isa/RVM.scala isa/RVZicsr.scala isa/RVZifencei.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/ram.cpp
99dd9207	23-Jun-2020	LinJiawei <[email protected]>	add decode buffer /XiangShan/.gitignore /XiangShan/build.sc /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Lsu.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/utils/MIMOQueue.scala
adc04fcb	22-Jun-2020	LinJiawei <[email protected]>	Brq/DecodeStage: chage MicroOp to CfCtrl /XiangShan/.github/workflows/core_ci.yml /XiangShan/Makefile /XiangShan/fpga/board/axu3cg/constr/hdmi.xdc /XiangShan/fpga/board/axu3cg/rtl/system_top.v /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/ram.cpp
9a2e6b8a	18-Jun-2020	LinJiawei <[email protected]>	Adjust pipeline, refactor EXU, IssueQueue /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala DecodeBuffer.scala DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/package.scala
5844fcf0	16-Jun-2020	LinJiawei <[email protected]>	Initially completed the module interface design /XiangShan/.gitignore /XiangShan/Makefile /XiangShan/README.md /XiangShan/build.sbt /XiangShan/build.sc /XiangShan/debug/.gitignore /XiangShan/debug/Makefile /XiangShan/devlog.md /XiangShan/fpga/Makefile /XiangShan/fpga/Makefile.check /XiangShan/fpga/board/axu3cg/bd/prm.tcl /XiangShan/fpga/board/axu3cg/constr/hdmi.xdc /XiangShan/fpga/board/axu3cg/mk.tcl /XiangShan/fpga/board/axu3cg/rtl/addr_mapper.v /XiangShan/fpga/board/axu3cg/rtl/hdmi/i2c_config.v /XiangShan/fpga/board/axu3cg/rtl/hdmi/i2c_master_bit_ctrl.v /XiangShan/fpga/board/axu3cg/rtl/hdmi/i2c_master_byte_ctrl.v /XiangShan/fpga/board/axu3cg/rtl/hdmi/i2c_master_defines.v /XiangShan/fpga/board/axu3cg/rtl/hdmi/i2c_master_top.v /XiangShan/fpga/board/axu3cg/rtl/hdmi/timescale.v /XiangShan/fpga/board/axu3cg/rtl/system_top.v /XiangShan/fpga/board/common.tcl /XiangShan/fpga/board/ultraZ/bd/prm.tcl /XiangShan/fpga/board/ultraZ/constr/constr.xdc /XiangShan/fpga/board/ultraZ/mk.tcl /XiangShan/fpga/board/ultraZ/rtl/addr_mapper.v /XiangShan/fpga/board/ultraZ/rtl/system_top.v /XiangShan/fpga/board/zedboard/bd/prm.tcl /XiangShan/fpga/board/zedboard/constr/constr.xdc /XiangShan/fpga/board/zedboard/constr/vga.xdc /XiangShan/fpga/board/zedboard/mk.tcl /XiangShan/fpga/board/zedboard/rtl/addr_mapper.v /XiangShan/fpga/board/zedboard/rtl/system_top.v /XiangShan/fpga/boot/.gitignore /XiangShan/fpga/boot/README.md /XiangShan/fpga/boot/axu3cg/u-boot.elf /XiangShan/fpga/boot/bootgen-zynq.bif /XiangShan/fpga/boot/bootgen-zynqmp.bif /XiangShan/fpga/boot/bug-list.md /XiangShan/fpga/boot/mk.tcl /XiangShan/fpga/lib/include/axi.vh /XiangShan/fpga/noop.tcl /XiangShan/fpga/resource/ddr-loader/ddr-loader.c /XiangShan/project/build.properties /XiangShan/scalastyle-config.xml /XiangShan/scalastyle-test-config.xml /XiangShan/scripts/vlsi_mem_gen /XiangShan/src/main/scala/bus/axi4/AXI4.scala /XiangShan/src/main/scala/bus/axi4/Delayer.scala /XiangShan/src/main/scala/bus/simplebus/Crossbar.scala /XiangShan/src/main/scala/bus/simplebus/DistributedMem.scala /XiangShan/src/main/scala/bus/simplebus/SimpleBus.scala /XiangShan/src/main/scala/bus/simplebus/ToAXI4.scala /XiangShan/src/main/scala/device/AXI4DummySD.scala /XiangShan/src/main/scala/device/AXI4Flash.scala /XiangShan/src/main/scala/device/AXI4Keyboard.scala /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/device/AXI4Slave.scala /XiangShan/src/main/scala/device/AXI4Timer.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/device/AXI4VGA.scala /XiangShan/src/main/scala/fpu/Classify.scala /XiangShan/src/main/scala/fpu/F32toF64.scala /XiangShan/src/main/scala/fpu/F64toF32.scala /XiangShan/src/main/scala/fpu/FCMP.scala /XiangShan/src/main/scala/fpu/FMV.scala /XiangShan/src/main/scala/fpu/FPUSubModule.scala /XiangShan/src/main/scala/fpu/FloatToInt.scala /XiangShan/src/main/scala/fpu/IntToFloat.scala /XiangShan/src/main/scala/fpu/README.md /XiangShan/src/main/scala/fpu/RoundingUnit.scala /XiangShan/src/main/scala/fpu/divsqrt/DivSqrt.scala /XiangShan/src/main/scala/fpu/divsqrt/MantDivSqrt.scala /XiangShan/src/main/scala/fpu/divsqrt/OnTheFlyConv.scala /XiangShan/src/main/scala/fpu/divsqrt/SrtTable.scala /XiangShan/src/main/scala/fpu/fma/ArrayMultiplier.scala /XiangShan/src/main/scala/fpu/fma/FMA.scala /XiangShan/src/main/scala/fpu/fma/LZA.scala /XiangShan/src/main/scala/fpu/package.scala /XiangShan/src/main/scala/fpu/util/CarrySaveAdder.scala /XiangShan/src/main/scala/fpu/util/FPUDebug.scala /XiangShan/src/main/scala/fpu/util/ORTree.scala /XiangShan/src/main/scala/fpu/util/ShiftLeftJam.scala /XiangShan/src/main/scala/fpu/util/ShiftRightJam.scala /XiangShan/src/main/scala/gpu/GPU.scala /XiangShan/src/main/scala/noop/BPU.scala /XiangShan/src/main/scala/noop/Bundle.scala /XiangShan/src/main/scala/noop/Cache.scala /XiangShan/src/main/scala/noop/Decode.scala /XiangShan/src/main/scala/noop/EXU.scala /XiangShan/src/main/scala/noop/IDU1.scala /XiangShan/src/main/scala/noop/IDU2.scala /XiangShan/src/main/scala/noop/IFU.scala /XiangShan/src/main/scala/noop/ISU.scala /XiangShan/src/main/scala/noop/NOOP.scala /XiangShan/src/main/scala/noop/NOOPTrap.scala /XiangShan/src/main/scala/noop/TLB.scala /XiangShan/src/main/scala/noop/WBU.scala /XiangShan/src/main/scala/noop/fu/ALU.scala /XiangShan/src/main/scala/noop/fu/CSR.scala /XiangShan/src/main/scala/noop/fu/FPU.scala /XiangShan/src/main/scala/noop/fu/LSU.scala /XiangShan/src/main/scala/noop/fu/MDU.scala /XiangShan/src/main/scala/noop/fu/MOU.scala /XiangShan/src/main/scala/noop/isa/Priviledged.scala /XiangShan/src/main/scala/noop/isa/RVA.scala /XiangShan/src/main/scala/noop/isa/RVC.scala /XiangShan/src/main/scala/noop/isa/RVD.scala /XiangShan/src/main/scala/noop/isa/RVF.scala /XiangShan/src/main/scala/noop/isa/RVI.scala /XiangShan/src/main/scala/noop/isa/RVM.scala /XiangShan/src/main/scala/noop/isa/RVZicsr.scala /XiangShan/src/main/scala/noop/isa/RVZifencei.scala /XiangShan/src/main/scala/system/Coherence.scala /XiangShan/src/main/scala/system/Prefetcher.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/TopMain.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/Debug.scala /XiangShan/src/main/scala/utils/FlushableQueue.scala /XiangShan/src/main/scala/utils/GTimer.scala /XiangShan/src/main/scala/utils/Hold.scala /XiangShan/src/main/scala/utils/LFSR64.scala /XiangShan/src/main/scala/utils/LatencyPipe.scala /XiangShan/src/main/scala/utils/Lock.scala /XiangShan/src/main/scala/utils/LookupTree.scala /XiangShan/src/main/scala/utils/Pipeline.scala /XiangShan/src/main/scala/utils/RegMap.scala /XiangShan/src/main/scala/utils/SRAMTemplate.scala /XiangShan/src/main/scala/utils/StopWatch.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala DecodeStage.scala Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueStage.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeIFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/utils/BitUtils.scala /XiangShan/src/main/scala/xiangshan/utils/Debug.scala /XiangShan/src/main/scala/xiangshan/utils/FlushableQueue.scala /XiangShan/src/main/scala/xiangshan/utils/GTimer.scala /XiangShan/src/main/scala/xiangshan/utils/Hold.scala /XiangShan/src/main/scala/xiangshan/utils/LFSR64.scala /XiangShan/src/main/scala/xiangshan/utils/LatencyPipe.scala /XiangShan/src/main/scala/xiangshan/utils/Lock.scala /XiangShan/src/main/scala/xiangshan/utils/LookupTree.scala /XiangShan/src/main/scala/xiangshan/utils/ParallelMux.scala /XiangShan/src/main/scala/xiangshan/utils/Pipeline.scala /XiangShan/src/main/scala/xiangshan/utils/RegMap.scala /XiangShan/src/main/scala/xiangshan/utils/SRAMTemplate.scala /XiangShan/src/main/scala/xiangshan/utils/StopWatch.scala /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/device.cpp /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/keyboard.cpp /XiangShan/src/test/csrc/macro.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/monitor.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/sdcard.cpp /XiangShan/src/test/csrc/uart.cpp /XiangShan/src/test/csrc/vga.cpp /XiangShan/src/test/scala/cache/CacheTest.scala /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/vsrc/monitor.v /XiangShan/src/test/vsrc/ram.v /XiangShan/tools/readmemh/Makefile /XiangShan/tools/readmemh/gen-treadle-readmemh.c /XiangShan/tools/readmemh/groupby-4byte.c /XiangShan/tools/readmemh/split-readmemh.c
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