decode - OpenGrok history log for /XiangShan/src/main/scala/xiangshan/backend/decode

Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
c0a38632	01-Dec-2020	Yinan Xu <[email protected]>	brq: allow enqueue i when there're i empty entries /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala DecodeStage.scala
4eb05fe2	01-Dec-2020	Yinan Xu <[email protected]>	brq: allow enqueue when #emptyEntries > enqnum /XiangShan/Makefile /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/ram.cpp
be25371a	30-Nov-2020	YikeZhou <[email protected]>	DecodeUnit: Add a rocket-like decode frame Bundle: Add `decode` method to CtrlSignals Bundle /XiangShan/src/main/scala/xiangshan/Bundle.scala DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/test/csrc/ram.cpp
20350a44	29-Nov-2020	Yinan Xu <[email protected]>	decodeBuffer: fix out.valid DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/test/csrc/ram.cpp
6a9a0533	29-Nov-2020	Yinan Xu <[email protected]>	dispatch1: block valid when blockBackward or noSpecExec /XiangShan/.github/workflows/emu.yml /XiangShan/.gitignore /XiangShan/.gitmodules /XiangShan/Makefile /XiangShan/block-inclusivecache-sifive /XiangShan/build.sc /XiangShan/chiseltest /XiangShan/rocket-chip /XiangShan/src/main/resources/vsrc/regfile_160x64_10w16r_sim.v /XiangShan/src/main/scala/device/AXI4SlaveModule.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FloatBlock.scala /XiangShan/src/main/scala/xiangshan/backend/IntegerBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/L1plusCache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/ram.h /XiangShan/src/test/csrc/snapshot.h /XiangShan/src/test/scala/cache/UnalignedGetTest.scala /XiangShan/src/test/scala/top/XSSim.scala
2d366136	21-Nov-2020	LinJiawei <[email protected]>	Decode: split 'noSpecExec' and 'blockBackward' noSpecExec can only enq roq when roq is empty blockBackward should block roq when the instruction is not commited /XiangShan/.github/workflows/check-usage.sh /XiangShan/.github/workflows/emu.yml /XiangShan/.gitignore /XiangShan/.gitmodules /XiangShan/Makefile /XiangShan/api-config-chipsalliance /XiangShan/berkeley-hardfloat /XiangShan/block-inclusivecache-sifive /XiangShan/build.sc /XiangShan/chisel3 /XiangShan/chiseltest /XiangShan/debug/Makefile /XiangShan/debug/cputest.sh /XiangShan/debug/sc_stat.sh /XiangShan/firrtl /XiangShan/rocket-chip /XiangShan/src/main/scala/device/AXI4DummySD.scala /XiangShan/src/main/scala/device/AXI4Flash.scala /XiangShan/src/main/scala/device/AXI4Keyboard.scala /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/device/AXI4SlaveModule.scala /XiangShan/src/main/scala/device/AXI4Timer.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/device/AXI4VGA.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Parameters.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/ParallelMux.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FloatBlock.scala /XiangShan/src/main/scala/xiangshan/backend/IntegerBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wb.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Radix2Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/F32toF64.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/F64toF32.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FCMP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMV.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FloatToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFloat.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFloatSingleCycle.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/divsqrt/DivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/fma/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/L1plusCache.scala /XiangShan/src/main/scala/xiangshan/cache/atomics.scala /XiangShan/src/main/scala/xiangshan/cache/atomicsMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/icacheMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/ldu.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/storeMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/uncache.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/snapshot.cpp /XiangShan/src/test/csrc/snapshot.h /XiangShan/src/test/scala/cache/CacheTest.scala /XiangShan/src/test/scala/cache/L1plusCacheTest.scala /XiangShan/src/test/scala/cache/L2CacheNonInclusiveGetTest.scala /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/device/AXI4BurstMaster.scala /XiangShan/src/test/scala/device/AXI4RamTest.scala /XiangShan/src/test/scala/device/AXI4TimerTest.scala /XiangShan/src/test/scala/device/SimMMIOTest.scala /XiangShan/src/test/scala/device/TLTimerTest.scala /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala /XiangShan/src/test/scala/xiangshan/frontend/PDtest.scala /XiangShan/src/test/scala/xiangshan/frontend/RASTest.scala /XiangShan/src/test/scala/xiangshan/frontend/uBTBTest.scala /XiangShan/src/test/scala/xiangshan/memend/SbufferTest.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala /XiangShan/src/test/vsrc/ram.v /XiangShan/treadle
ef74f7cb	02-Nov-2020	LinJiawei <[email protected]>	Merge remote-tracking branch 'origin/fix-boringutils' into xs-fpu /XiangShan/.github/workflows/emu.yml /XiangShan/.gitmodules /XiangShan/Makefile /XiangShan/block-inclusivecache-sifive /XiangShan/build.sc /XiangShan/chiseltest /XiangShan/debug/Makefile /XiangShan/rocket-chip /XiangShan/src/main/scala/device/AXI4Timer.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/device/TLTimer.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/utils/CircularQueuePtr.scala /XiangShan/src/main/scala/utils/SRAMTemplate.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/DivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/I2fExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/atomics.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/probe.scala /XiangShan/src/main/scala/xiangshan/cache/wbu.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/separated/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/separated/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/separated/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/unified/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xstransforms/PrintModuleName.scala /XiangShan/src/main/scala/xstransforms/ShowPrintTransform.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/sdcard.cpp /XiangShan/src/test/csrc/sdcard.h /XiangShan/src/test/csrc/uart.cpp /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/xiangshan/testutils/TestCaseGenerator.scala
da10912f	02-Nov-2020	Yinan Xu <[email protected]>	src: remove unused import BoringUtils /XiangShan/.github/workflows/emu.yml /XiangShan/.gitmodules /XiangShan/Makefile /XiangShan/block-inclusivecache-sifive /XiangShan/build.sc /XiangShan/chiseltest /XiangShan/debug/Makefile /XiangShan/debug/perf_sbuffer.sh /XiangShan/rocket-chip /XiangShan/src/main/scala/device/AXI4Timer.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/device/TLTimer.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/utils/CircularQueuePtr.scala /XiangShan/src/main/scala/utils/SRAMTemplate.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/DivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/atomics.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/probe.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/wbu.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/separated/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/separated/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/separated/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/unified/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xstransforms/PrintModuleName.scala /XiangShan/src/main/scala/xstransforms/ShowPrintTransform.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/sdcard.cpp /XiangShan/src/test/csrc/sdcard.h /XiangShan/src/test/csrc/uart.cpp /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/xiangshan/testutils/TestCaseGenerator.scala
1131ca11	13-Oct-2020	LinJiawei <[email protected]>	[WIP] Merge debian-gogogo into xs-fpu /XiangShan/Makefile /XiangShan/debug/perf_sbuffer.sh /XiangShan/src/main/scala/device/TLTimer.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala isa/Privileged.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/wbu.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/mem/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/FakeSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/Sbuffer.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/sdcard.cpp /XiangShan/src/test/scala/top/XSSim.scala
f463285d	09-Oct-2020	Yinan Xu <[email protected]>	rvc: disable C_F floating-point instructions /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile /XiangShan/src/main/scala/utils/StopWatch.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala isa/RVC.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/cache/L1Cache.scala /XiangShan/src/main/scala/xiangshan/cache/atomics.scala /XiangShan/src/main/scala/xiangshan/cache/atomicsMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/ldu.scala /XiangShan/src/main/scala/xiangshan/cache/loadMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/storeMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/stu.scala /XiangShan/src/main/scala/xiangshan/cache/uncache.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/Sbuffer.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/scala/top/XSSim.scala
b03ab6c3	29-Sep-2020	linjiawei <[email protected]>	FPU: Make hasFPU configurable /XiangShan/.github/workflows/emu.yml /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/utils/StopWatch.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/cache/L1Cache.scala /XiangShan/src/main/scala/xiangshan/cache/atomics.scala /XiangShan/src/main/scala/xiangshan/cache/atomicsMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/ldu.scala /XiangShan/src/main/scala/xiangshan/cache/loadMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/storeMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/stu.scala /XiangShan/src/main/scala/xiangshan/cache/uncache.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/Sbuffer.scala /XiangShan/src/main/scala/xstransforms/ShowPrintTransform.scala
b853a371	28-Sep-2020	linjiawei <[email protected]>	FPU: support rvc Decoder.scala isa/RVC.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala
a63fed5b	28-Sep-2020	linjiawei <[email protected]>	FPU: riscv-test pass /XiangShan/Makefile Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/I2fExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala
3aa40062	28-Sep-2020	linjiawei <[email protected]>	Exu: fix output /XiangShan/src/main/scala/xiangshan/Bundle.scala Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/I2fExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala
921f5f97	28-Sep-2020	Yinan Xu <[email protected]>	decode: do not enable f and d extentions if not hasFPU /XiangShan/Makefile /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/utils/LogUtils.scala DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xstransforms/PrintModuleName.scala /XiangShan/src/main/scala/xstransforms/ShowPrintTransform.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/scala/top/XSSim.scala
304b8afd	26-Sep-2020	linjiawei <[email protected]>	decode: fix fpu decode /XiangShan/Makefile /XiangShan/debug/Makefile /XiangShan/ready-to-run/bbl.bin /XiangShan/ready-to-run/linux.bin /XiangShan/ready-to-run/microbench.bin /XiangShan/ready-to-run/riscv64-nemu-interpreter-so /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/ParallelMux.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala Decoder.scala isa/RVC.scala isa/RVD.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/I2fExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFloatSingleCycle.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/divsqrt/DivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/package.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/L1Cache.scala /XiangShan/src/main/scala/xiangshan/cache/atomics.scala /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/ldu.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/stu.scala /XiangShan/src/main/scala/xiangshan/cache/uncache.scala /XiangShan/src/main/scala/xiangshan/cache/wbu.scala /XiangShan/src/main/scala/xiangshan/mem/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/Sbuffer.scala /XiangShan/src/main/scala/xstransforms/PrintModuleName.scala /XiangShan/src/main/scala/xstransforms/ShowPrintTransform.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/scala/top/XSSim.scala
98234405	24-Sep-2020	LinJiawei <[email protected]>	Backend: decode WFI /XiangShan/Makefile /XiangShan/debug/Makefile /XiangShan/logfix.c /XiangShan/ready-to-run/bbl.bin /XiangShan/ready-to-run/linux.bin /XiangShan/ready-to-run/microbench.bin /XiangShan/ready-to-run/riscv64-nemu-interpreter-so /XiangShan/src/main/scala/device/TLTimer.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala isa/Privileged.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/L1Cache.scala /XiangShan/src/main/scala/xiangshan/cache/atomics.scala /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/ldu.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/stu.scala /XiangShan/src/main/scala/xiangshan/cache/uncache.scala /XiangShan/src/main/scala/xiangshan/cache/wbu.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/mem/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/sdcard.cpp /XiangShan/src/test/scala/top/XSSim.scala
86ae72a0	20-Sep-2020	LinJiawei <[email protected]>	Decoder[WIP]: add floating point instructions' decode Decoder.scala isa/RVD.scala isa/RVF.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
7a794e79	19-Sep-2020	LinJiawei <[email protected]>	LoadUnit: support flw /XiangShan/debug/Makefile /XiangShan/src/main/scala/device/TLTimer.scala /XiangShan/src/main/scala/noop/fu/FPU.scala /XiangShan/src/main/scala/noop/fu/LSU.scala /XiangShan/src/main/scala/noop/isa/RVD.scala /XiangShan/src/main/scala/noop/isa/RVF.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/exu/DivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmiscDivSqrtExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fmac.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fmisc.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/I2f.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/Classify.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/F32toF64.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/F64toF32.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FCMP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMV.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FloatToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFloat.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/README.md /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/RoundingUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/divsqrt/DivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/divsqrt/MantDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/divsqrt/OnTheFlyConv.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/divsqrt/SrtTable.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/fma/ArrayMultiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/fma/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/fma/LZA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/package.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/util/CarrySaveAdder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/util/FPUDebug.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/util/ORTree.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/util/ShiftLeftJam.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/util/ShiftRightJam.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/atomics.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/mem/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/scala/top/XSSim.scala
40f79903	10-Sep-2020	Yinan Xu <[email protected]>	decode: mret, sret as branch instruction and need brTag /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/mem/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/StoreUnit.scala /XiangShan/src/test/csrc/difftest.cpp
37958a77	09-Sep-2020	Allen <[email protected]>	Membackend: removed the duplicated LSUOpType. isa/RVA.scala /XiangShan/src/main/scala/xiangshan/mem/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala
fa4683cc	09-Sep-2020	Allen <[email protected]>	Atomics: deal with atomcis w and d. /XiangShan/.gitmodules /XiangShan/block-inclusivecache-sifive /XiangShan/build.sc /XiangShan/debug/Makefile /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/utils/DebugIdentityNode.scala /XiangShan/src/main/scala/utils/TLDump.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala isa/RVA.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/atomics.scala /XiangShan/src/main/scala/xiangshan/cache/atomicsMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/ldu.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/probe.scala /XiangShan/src/main/scala/xiangshan/cache/stu.scala /XiangShan/src/main/scala/xiangshan/cache/wbu.scala /XiangShan/src/main/scala/xiangshan/mem/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/Sbuffer.scala /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala
58d40d0c	06-Sep-2020	ZhangZifei <[email protected]>	Roq: replace csr's non spec exe with noSepcExec for csr/fence/atomic isa/RVZifencei.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala
9fb9eb47	06-Sep-2020	ZhangZifei <[email protected]>	Fence: fix bug of isa bitmap of fence instr /XiangShan/src/main/scala/xiangshan/backend/Backend.scala isa/Privileged.scala isa/RVZifencei.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala
45a56a29	05-Sep-2020	ZhangZifei <[email protected]>	Roq: add flush pipe logic for fence instr /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/DivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/LsExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala
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