decode - OpenGrok history log for /XiangShan/src/main/scala/xiangshan/backend/decode

Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
72d89280	10-Apr-2023	Xuan Hu <[email protected]>	backend: add float inst support /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/ctrlblock/MemCtrl.scala /XiangShan/src/main/scala/xiangshan/backend/ctrlblock/RedirectGenerator.scala DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Bku.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Branch.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xiangshan/v2backend/Backend.scala /XiangShan/src/main/scala/xiangshan/v2backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/v2backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/v2backend/DataPath.scala /XiangShan/src/main/scala/xiangshan/v2backend/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/v2backend/RegFile.scala /XiangShan/src/main/scala/xiangshan/v2backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/v2backend/dispatch/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/v2backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/v2backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/v2backend/fu/BranchUnit.scala /XiangShan/src/main/scala/xiangshan/v2backend/fu/DivUnit.scala /XiangShan/src/main/scala/xiangshan/v2backend/fu/FuncUnit.scala /XiangShan/src/main/scala/xiangshan/v2backend/fu/JumpUnit.scala /XiangShan/src/main/scala/xiangshan/v2backend/fu/MulUnit.scala /XiangShan/src/main/scala/xiangshan/v2backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/v2backend/issue/StatusArray.scala /XiangShan/src/main/scala/xiangshan/v2backend/package.scala
fbc24a91	05-Apr-2023	czw <[email protected]>	func(UopDivType): support VEC_SLIDEUP/VEC_ISLIDEUP/VEC_SLIDEDOWN/VEC_ISLIDEDOWN (#2028) * func(UopDivType): support VEC_SLIDEUP/VEC_ISLIDEUP/VEC_SLIDEDOWN/VEC_ISLIDEDOWN * pom(yunsuan): add isVsild func(UopDivType): support VEC_SLIDEUP/VEC_ISLIDEUP/VEC_SLIDEDOWN/VEC_ISLIDEDOWN (#2028) * func(UopDivType): support VEC_SLIDEUP/VEC_ISLIDEUP/VEC_SLIDEDOWN/VEC_ISLIDEDOWN * pom(yunsuan): add isVsilde in VpermType & fix bugs of Permutation show more ... /XiangShan/src/main/scala/xiangshan/Parameters.scala DecodeUnitComp.scala VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VPerm.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/yunsuan
40767ba3	03-Apr-2023	xiaofeibao-xjtu <[email protected]>	func(vfpu): add VfpuType VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VFPU.scala /XiangShan/yunsuan
b8298242	02-Apr-2023	czw <[email protected]>	func(DecodeUnitComp): support VEC_VRED (#2017) * func(DecodeUnitComp): support VEC_VRED of UopDivType * fix(vxsat):fix bug that VPU's vxsat shout be arbitrated * pom(yunsuan):fix Decode of vmvsx & func(DecodeUnitComp): support VEC_VRED (#2017) * func(DecodeUnitComp): support VEC_VRED of UopDivType * fix(vxsat):fix bug that VPU's vxsat shout be arbitrated * pom(yunsuan):fix Decode of vmvsx & add some test for VPERM show more ... /XiangShan/src/main/scala/xiangshan/Parameters.scala DecodeUnitComp.scala VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VFPU.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/yunsuan
4365a7a7	31-Mar-2023	czw <[email protected]>	func(DecodeUnitComp) : support vfslide1up & vslide1down & vfslide1down (#2012) * func(DecodeUnitComp): support vfslide1up.vf * func(DecodeUnitComp):support vslide1down & vfslide1down * pom(yunsuan func(DecodeUnitComp) : support vfslide1up & vslide1down & vfslide1down (#2012) * func(DecodeUnitComp): support vfslide1up.vf * func(DecodeUnitComp):support vslide1down & vfslide1down * pom(yunsuan):add vfslide1up & vfslide1down 1. func(VFMA):add vfmsac, vfnmsac, vfmadd, vfnmadd, vfmsub, vfnmsub, vfwmul, vfwmacc, vfwnmacc, vfwmsac, vfwnmsac and their test supports 2. func(VpermType): add vfslide1up & vfslide1down show more ... /XiangShan/ready-to-run /XiangShan/src/main/scala/xiangshan/Parameters.scala DecodeStage.scala DecodeUnitComp.scala VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VFPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VPerm.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/yunsuan
de9e1949	28-Mar-2023	czw <[email protected]>	pom(yunsuan): add IALU V3 (#2004) 1. func(VPERM): fix tail process, optimize vcompress, change vslide module name 2. func(VPERM): change to 2-stage 3. test(VPERM): add golden model and test: vslid pom(yunsuan): add IALU V3 (#2004) 1. func(VPERM): fix tail process, optimize vcompress, change vslide module name 2. func(VPERM): change to 2-stage 3. test(VPERM): add golden model and test: vslidedown 4. test(VPERM): set vxsat=0 for vperm 5. test(VFADD): support vector-scalar operations func(VFADD): support vector-scalar operations 6. test: include 7. func(VFMA): add input:op_code,frs1,is_frs1; support vfmul.vv 8. func(VFMA):add vfmul.vf vfnmacc.vv vfnmacc.vf and their test supports 9. func(IALU):add IALU V3 * fix(decode): fix decode bug of selImm 1. fix decode bug of selImm 2. change VipuType to VpermType * func(yunsuan): add VIAlu code v3 1. add VIAlu code v3 2. Update the IO of VFPU * pom(yunsuan): add IALU V3 1. func(VPERM): fix tail process, optimize vcompress, change vslide module name 2. func(VPERM): change to 2-stage 3. test(VPERM): add golden model and test: vslidedown 4. test(VPERM): set vxsat=0 for vperm 5. test(VFADD): support vector-scalar operations func(VFADD): support vector-scalar operations 6. test: include <algorithm> 7. func(VFMA): add input:op_code,frs1,is_frs1; support vfmul.vv 8. func(VFMA):add vfmul.vf vfnmacc.vv vfnmacc.vf and their test supports 9. func(IALU):add IALU V3 show more ... DecodeUnitComp.scala VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VFPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VPerm.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/yunsuan
2f2537e9	24-Mar-2023	czw <[email protected]>	fix(selImm): fix selImm bug of OPIVI inst (#1998) VecDecoder.scala /XiangShan/yunsuan
4b4fcc4b	24-Mar-2023	zhanglyGit <[email protected]>	fix(vsetvl): fix bug of vsetvl 'flushpipe' generating (#1993) DecodeUnitComp.scala
7e79df6b	23-Mar-2023	zhanglyGit <[email protected]>	decode: support tail undisturbed DecodeUnitComp.scala VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VFPU.scala
b238ab97	22-Mar-2023	zhanglyGit <[email protected]>	func(vslide1up): support vslide1up instruction (#1990) * func(decode+VIPU): support vslide1up instruction * bump(yunsuan): func(VFADD) & VIPU type & test(VPERM) DecodeUnitComp.scala VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/yunsuan
5ef600c3	22-Mar-2023	zhanglyGit <[email protected]>	fix(decode): fix bug of decodeUnitComp(stateReg) (#1989) DecodeUnitComp.scala
12797c73	20-Mar-2023	czw <[email protected]>	style(DecodeUnitComp): optimize code style of DecodeUnitComp DecodeUnitComp.scala /XiangShan/yunsuan
876aa65b	20-Mar-2023	czw <[email protected]>	refactor(VIPU): optimize decoding logic of VIPU 1. Some logic moves from VIPU.scala to VPUSubModule.scala 2. add VIAluFix DecodeStage.scala VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VPUSubModule.scala /XiangShan/src/main/scala/xiangshan/package.scala
c21d79b9	19-Mar-2023	czw <[email protected]>	style(INT_VCONFIG): add parameter INT_VCONFIG /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala DecodeStage.scala DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
397c4261	20-Mar-2023	zhanglyGit <[email protected]>	decode: parameter style optimization (#1985) DecodeUnitComp.scala
19d2cf8f	20-Mar-2023	zhanglyGit <[email protected]>	fix(decode): fpwen consistent(uop-div) (#1983) DecodeUnitComp.scala
f5e33eee	19-Mar-2023	czw <[email protected]>	fix(vset): fix vset bug that writing vconfig need the condition of rfWen==true (#1982) /XiangShan/.github/workflows/emu.yml /XiangShan/.github/workflows/nightly.yml /XiangShan/build.sc /XiangShan/debug/local_ci.py /XiangShan/difftest /XiangShan/huancun /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/utils/ArbiterHelper.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala DecodeStage.scala DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/utility
c4f96a91	17-Mar-2023	czw <[email protected]>	refactor(UopDivType): rename UopDivType & change VECTOR_TMP_REG_MV to FP_TMP_REG_MV 1. rename UopDivType 2. change VECTOR_TMP_REG_MV to FP_TMP_REG_MV 3. add UopDivType.VEC_MMM for decode of VMAND_MM refactor(UopDivType): rename UopDivType & change VECTOR_TMP_REG_MV to FP_TMP_REG_MV 1. rename UopDivType 2. change VECTOR_TMP_REG_MV to FP_TMP_REG_MV 3. add UopDivType.VEC_MMM for decode of VMAND_MM VMANDN_MM ... VMXOR_MM show more ... DecodeUnit.scala DecodeUnitComp.scala VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/yunsuan
1e160ed8	17-Mar-2023	zhanglyGit <[email protected]>	decode: support mask instrutions UOP_DIV (#1975) DecodeUnitComp.scala VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala /XiangShan/src/main/scala/xiangshan/package.scala
c5d30ea7	16-Mar-2023	zhanglyGit <[email protected]>	decode: fix narrowing instrutions bugs(uop-div) (#1972) /XiangShan/src/main/scala/xiangshan/Parameters.scala DecodeStage.scala DecodeUnitComp.scala VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala
80f76ebc	15-Mar-2023	czw <[email protected]>	func(vfmin vfmax): pass vfmin & vfmax in VectorFloatAdder VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VFPU.scala /XiangShan/yunsuan
89922465	13-Mar-2023	czw <[email protected]>	func(VipuType): add VipuType of vwsubu.vv vwsubu.wv vwsub.vx vwsub.wx /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FUBlock.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationBase.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
5d9d92aa	15-Mar-2023	zhanglyGit <[email protected]>	decode: support widening/narrowing/vsext/vzext instructions uop-div (#1963) /XiangShan/ready-to-run DecodeUnit.scala DecodeUnitComp.scala VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala /XiangShan/src/main/scala/xiangshan/package.scala
f9cac32f	13-Mar-2023	czw <[email protected]>	func(decode):add VIAlu decode of VecDecoder & VIPU 1. fix bug that connection of fuOpType in VIPU 2. vadd vmin vminu vmax vmaxu vand vor vxor vsub vrsub test pass /XiangShan/difftest VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala /XiangShan/yunsuan
3d1a5c10	11-Mar-2023	maliao <[email protected]>	Rob: Add Rab module to support separate commit of uops and instructions (#1956) /XiangShan/difftest /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala DecodeUnit.scala DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationBase.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/package.scala
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