feat(zvfh,zfh): add F16 support

fix(zfh): flh/fsh should raise illegal exception when fs is off.

feat(zihintpause): support zihintpause

feat(decode): no rob compress when is last in ftq

set canRobCompress to false when a instruction is the last one in
its Ftq entry.

fix(vtypegen): block the decode until vtype is recovered from walk (#3705)

fix(vector, decode): use OPFV[VF] encoded in inst to check if need FS not Off (#3696)

* When FS is Off, executing vfslide1up/down should raise illegal instruction exception

feat(rv64v): support first only fault instruction

feat(rv64v): support vleff instruction in backend

* use the last uop to update vl
* the vleff instructions are run inorder

fix(vtypegen): fix initial condition after receive redirect (#3664)

feat(Zicbom,Zicboz): add permission check and convert CBO.INVAL to CBO.FLUSH when CBIE=0b01 (#3559)

* CSR
* When reset, xenvcfg.CBZE = 1, xenvcfg.CBCFE = 1, xenvcfg.CBIE = 0b11,
while x in {m, s,

feat(Zicbom,Zicboz): add permission check and convert CBO.INVAL to CBO.FLUSH when CBIE=0b01 (#3559)

* CSR
* When reset, xenvcfg.CBZE = 1, xenvcfg.CBCFE = 1, xenvcfg.CBIE = 0b11,
while x in {m, s, h}.
* Support xenvcfg.CBIE = Flush(0b01)
* Decode
* Use the illegalInst and virtualInst conditions from CSR to assert
EX_II or EX_VI.
* Convert CBO.INVAL to CBO.FLUSH when envcfg.CBIE === EnvCBIE.Flush.

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fix(Svinval): make all insts in Sinval behavior like fence to avoid software wrong usage (#3534)

* Since software cannot promiss all sinval.vma between sfence.w.inval
and sfence.inval.ir, we make s

fix(Svinval): make all insts in Sinval behavior like fence to avoid software wrong usage (#3534)

* Since software cannot promiss all sinval.vma between sfence.w.inval
and sfence.inval.ir, we make sinval.vma always wait forward.

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fix(vecException): fix float exception generate when sew <= 16 (#3535)

Backend: stop block_backward for csrr, in rename stage

accelerate read only csrr by pipelining

fix(rv64v): set vwredsum instructions always depend on oldvd (#3495)

* vwredsum's split type is UopSplitType.VEC_VWW

feat(VceExceptionGen): support Zvfhmin extension (#3493)

Cancel the exception of the Zvfhmin extension instruction and support Zvfhmin extension.

* The Zvfhmin extension refers to the case where

feat(VceExceptionGen): support Zvfhmin extension (#3493)

Cancel the exception of the Zvfhmin extension instruction and support Zvfhmin extension.

* The Zvfhmin extension refers to the case where sew==1, where the
exceptions for VFWCVT_F_F_V and VFNCVT_F_F_W instructions are removed.

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feat(riscv64): support RISC-V Smrnmi extension (#3480)

feat(riscv64): Support RISC-V Zfa extension

* Support fli.{h.s.d}, fminm.{h.s.d}, fmaxm.{h.s.d}
* Support fround.{h.s.d}, froundnx.{h.s.d}, fcvtmod.w.d
* Support fleq.{h.s.d}, fltq.{h.s.d}

feat(rv64): add Zimop extension support

* All MOP.R.n and MOP.RR.n only update rd with 0s. This would be changed when any MOP redefined by some other extensions.
* Define all MOP.R.n and MOP.RR.n se

feat(rv64): add Zimop extension support

* All MOP.R.n and MOP.RR.n only update rd with 0s. This would be changed when any MOP redefined by some other extensions.
* Define all MOP.R.n and MOP.RR.n seperated instruction name for future easier modification, since any one of MOP could be meaningful instruction in the future.
* If rd is not 0, mop instructions will convert to a move instruction, which move x0 to rd.
* If rd is 0, mop instructions will convert to a addi intruction, whose rs0 is x0 and imm is 0.

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Decode: don't pass illegal inst to TrapInstMod when out not ready

Decode: don't pass illegal inst to TrapInstMod when redirect occurs

* Delay one cycle to pass illegal inst to get better timing

Decode: pass the output inst of DecodeStage instead of DecodeUnit to TrapInstMod

* This commit fix the fault instruction pass to TrapInstMod, which must be valid and illegal.
* When there is a vecto

Decode: pass the output inst of DecodeStage instead of DecodeUnit to TrapInstMod

* This commit fix the fault instruction pass to TrapInstMod, which must be valid and illegal.
* When there is a vector instruction in DecodeStage, DecodeUnit may use the old vector config to decode it. This will cause wrong result of illegal check, since new config provided by the vset[i]vl[i] before the vector instruction will change the result.

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Decode: store inst in TrapInstMod when EX_VI occurs

* This commit fix the error that the instructions leading to virtual instruction exceptions are not stored in tval when trap occurs.

decode: merge frontend EX_II in DecodeUnit

* Illegal instruction exception from Frontend is missed in DecodeStage before this commit.

Frontend,Backend: add xxtvala support

* utils
* Add checkInputWidth function in NamedUInt to check if the UInt arg passed in has the same width as it defined.
* Frontend
* Pass the unexpanded in

Frontend,Backend: add xxtvala support

* utils
* Add checkInputWidth function in NamedUInt to check if the UInt arg passed in has the same width as it defined.
* Frontend
* Pass the unexpanded instruciton to IBuffer if the C extension 16 bits instruction is illegal.
* No need to use bypass illBuf, since the origin 16 bits instruction will be passed in the ctrlflow bundle.
* IBuffer
* Merge exceptionType and crossPageIPFFix into 3bit field, which type is IBufferExceptionType.
* IBufferExceptionType can hold illegal instruction exception.
* Backend
* CSROpType.ro is removed, since we can use rs1 and rd passed in imm field to distinguish CSRR and CSRW in CSR module.
* Create TrapInstMod to store the trap instruction and handle its update.

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