decode - OpenGrok history log for /XiangShan/src/main/scala/xiangshan/backend/decode

Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
395c8649	04-Jan-2024	Ziyue-Zhang <[email protected]>	rv64v: add f2v to remove all fs1 duplicate logic (#2613) * rv64v: add f2v to remove all fs1 duplicate logic * rv64v: use IntFPToVec module for i2v and f2v /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala DecodeUnit.scala DecodeUnitComp.scala FPDecoder.scala UopInfoGen.scala VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntFPToVec.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecNonPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala /XiangShan/src/main/scala/xiangshan/package.scala
71d4d0e5	29-Dec-2023	Ziyue Zhang <[email protected]>	rv64v: fix special uimm compute for vmsleu, vmsgtu and vsaddu VecDecoder.scala
904d2184	29-Dec-2023	Ziyue Zhang <[email protected]>	rv64v: fix vxsat and vd compute for fixed-point instruction /XiangShan/src/main/scala/utils/ClockGate.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/ctrlblock/MemCtrl.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala UopInfoGen.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
31c51290	28-Dec-2023	zhanglinjuan <[email protected]>	Fix bugs in exceptional stores (#2600) * VPPU: fix timing mismatch between isMvnr and data * STU,HYU,VSFlowQueue: add exceptionVec in store pipeline feedbacks * VSFlowQueue: add exception buff Fix bugs in exceptional stores (#2600) * VPPU: fix timing mismatch between isMvnr and data * STU,HYU,VSFlowQueue: add exceptionVec in store pipeline feedbacks * VSFlowQueue: add exception buffer to record exceptional vaddr * MemBlock: modify signal naming show more ... /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala DecodeUnit.scala DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgtu.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSFlowQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
caa15984	27-Dec-2023	Ziyue Zhang <[email protected]>	rv64v: fix vred instruction when lmul < 1 DecodeUnitComp.scala
4c4e2cd8	26-Dec-2023	Ziyue Zhang <[email protected]>	rv64v: fix vmvnr when vl = 0 VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VPPU.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VLFlowQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VLUopQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala /XiangShan/yunsuan
305e657e	04-Jan-2024	Xuan Hu <[email protected]>	RiscvInst: add vector load/store function /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/ctrlblock/RedirectGenerator.scala isa/bitfield/RiscvInst.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
b8505463	25-Dec-2023	Ziyue Zhang <[email protected]>	rv64v: fix vslide1up/down uop split DecodeUnitComp.scala
daae8f22	25-Dec-2023	Ziyue Zhang <[email protected]>	rv64v: fix vector move instruction /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecNonPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VPPU.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VLFlowQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VLUopQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VLWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSFlowQueue.scala /XiangShan/yunsuan
7c67decc	08-Dec-2023	Ziyue Zhang <[email protected]>	rv64v: fix vmv.s.x instruction /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala DecodeUnitComp.scala VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala
b466b7fb	15-Dec-2023	Xuan Hu <[email protected]>	backend: fix update of vtype in VTypeGen * There is no need to resume vtype when redirect coming. Only resume vtype when rob walking. VTypeGen.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VLUopQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSUopQueue.scala
36781b55	08-Dec-2023	Ziyue Zhang <[email protected]>	rv64v: fix numOfWB compute /XiangShan/Makefile /XiangShan/build.sc /XiangShan/difftest /XiangShan/scripts/top-down/.gitignore /XiangShan/scripts/top-down/README.md /XiangShan/scripts/top-down/configs.py /XiangShan/scripts/top-down/draw.py /XiangShan/scripts/top-down/resources/spec06_rv64gcb_o2_20m.json /XiangShan/scripts/top-down/top_down.py /XiangShan/scripts/top-down/utils.py /XiangShan/src/main/scala/device/AXI4DummySD.scala /XiangShan/src/main/scala/device/AXI4Flash.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/ctrlblock/LsInfo.scala UopInfoGen.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VLFlowQueue.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/utility
8241cb85	17-Dec-2023	Xuan Hu <[email protected]>	Merge remote-tracking branch 'upstream/master' into backendq /XiangShan/.github/CODEOWNERS /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile /XiangShan/README.md /XiangShan/build.sc /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/huancun /XiangShan/readme.zh-cn.md /XiangShan/scripts/sram_size_collect.py /XiangShan/scripts/xiangshan.py /XiangShan/src/chisel/main/scala/top/XiangShanStage.scala /XiangShan/src/chisel/main/scala/xiangshan/transforms/Helpers.scala /XiangShan/src/chisel/main/scala/xiangshan/transforms/PrintControl.scala /XiangShan/src/chisel/main/scala/xiangshan/transforms/PrintModuleName.scala /XiangShan/src/chisel/main/scala/xiangshan/types.scala /XiangShan/src/chisel/test/scala/xiangshan/types.scala /XiangShan/src/chisel3/main/scala/top/XiangShanStage.scala /XiangShan/src/chisel3/main/scala/xiangshan/transforms/PrintControl.scala /XiangShan/src/chisel3/main/scala/xiangshan/transforms/PrintModuleName.scala /XiangShan/src/chisel3/main/scala/xiangshan/types.scala /XiangShan/src/chisel3/test/scala/xiangshan/types.scala /XiangShan/src/main/scala/device/AXI4Memory.scala /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Generator.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/utils/PerfCounterUtils.scala /XiangShan/src/main/scala/utils/Trigger.scala /XiangShan/src/main/scala/xiangshan/L2Top.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSDts.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala FusionDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Vsetu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/FakeDCache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Composer.scala /XiangShan/src/main/scala/xiangshan/frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBankedArray.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala /XiangShan/src/main/scala/xiangshan/transforms/PrintControl.scala /XiangShan/src/test/scala/fu/IntDiv.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/src/test/scala/xiangshan/DecodeTest.scala /XiangShan/utility
cd2c45fe	06-Dec-2023	Ziyue Zhang <[email protected]>	rv64v: fix vcpop and vfirst instructions /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala DecodeUnitComp.scala UopInfoGen.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
9faa51af	01-Dec-2023	xiaofeibao-xjtu <[email protected]>	backend: remove renameOut pipeline /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala DecodeStage.scala DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
c3f16425	22-Nov-2023	xiaofeibao-xjtu <[email protected]>	remove rename and dispatch pipeline /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
b1712600	05-Dec-2023	Ziyue Zhang <[email protected]>	rv64v: support copy data directly use i2v * also fix some bugs for vwadd.w and vrgather.vi /XiangShan/src/main/scala/xiangshan/Bundle.scala DecodeUnitComp.scala VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToVec.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/package.scala
4cdab2a9	05-Dec-2023	Xuan Hu <[email protected]>	decode: fix uops of vset DecodeUnitComp.scala VecDecoder.scala /XiangShan/src/main/scala/xiangshan/package.scala
229ab603	05-Dec-2023	Xuan Hu <[email protected]>	decode: fix fuOpType of vset inst in DecodeUnitComp DecodeUnitComp.scala
c5f1351b	05-Dec-2023	Xuan Hu <[email protected]>	decode: fix riscv vector exception checker * The v0 overlap checking should be done in vector arith/mem insts /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/utils/ClockGate.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/ctrlblock/RedirectGenerator.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala VecExceptionGen.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
0de3199c	28-Nov-2023	sinsanction <[email protected]>	FusionDecoder: prevent fusion when inst2 rs1 == rs2 (#2466) (#2513) FusionDecoder.scala
f7af4c74	17-Nov-2023	chengguanghui <[email protected]>	Debug Module: cherry-pick debug module from nanhu /XiangShan/src/main/scala/device/RocketDebugWrapper.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/utils/BitsUtils.scala /XiangShan/src/main/scala/utils/Trigger.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/DebugCSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/Trigger.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/test/scala/top/SimTop.scala
7d9a777a	04-Dec-2023	Xuan Hu <[email protected]>	decode: add dontTouch in VecExceptionGen to make better verilog VecExceptionGen.scala
e25c13fa	23-Nov-2023	Xuan Hu <[email protected]>	decode: refactor decode stage * The first complex inst can be send into DecodeComp if it is empty. * VType in VTypeGen will be updated when vset inst entering DecodeComp. * If there are left uops in decode: refactor decode stage * The first complex inst can be send into DecodeComp if it is empty. * VType in VTypeGen will be updated when vset inst entering DecodeComp. * If there are left uops in decodeComp, the count of rename ready uops will be send to rename stage. show more ... /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala DecodeStage.scala DecodeUnit.scala DecodeUnitComp.scala UopInfoGen.scala VTypeGen.scala VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VLFlowQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VLUopQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSFlowQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSUopQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala /XiangShan/src/main/scala/xiangshan/package.scala
06cb2bc1	17-Nov-2023	weidingliu <[email protected]>	rv64v：fix bug of load whole register (#2485) * decode:fix decode of vsr/vlre* Co-authored-by: Ziyue Zhang <[email protected]> * UopQueue: fix bug in nfields and emul in store/load rv64v：fix bug of load whole register (#2485) * decode:fix decode of vsr/vlre* Co-authored-by: Ziyue Zhang <[email protected]> * UopQueue: fix bug in nfields and emul in store/load whole register --------- Co-authored-by: Ziyue Zhang <[email protected]> show more ... /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala DecodeUnit.scala UopInfoGen.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VLFlowQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VLUopQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSFlowQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSUopQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
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