rv64v: fix some bugs in vector exception check

rv64v: fix the wrong dependency caused by uop split

vl: convert read vl instruction to a move instrcuction

* using vset module to move vl from vl register to int register

vset: fix old vl read for vsetvl and vsetvli instructions (#3058)

VPU: new vcompress to fit v0&vl split; fix vfredsum/min/max (#3053)

fix vfredsum/max/min:
When the vector vfredusum/max/min consists entirely of inactive elements
and vs1[0] is NaN, the result sho

VPU: new vcompress to fit v0&vl split; fix vfredsum/min/max (#3053)

fix vfredsum/max/min:
When the vector vfredusum/max/min consists entirely of inactive elements
and vs1[0] is NaN, the result should be vs1[0]
When both elements of vfredusum are inactive, the temporary result
changes from positive zero to negative zero.
nes vcompress to fit v0/vl split:
The vcompress calculation combines the ones_sum result with vs1 using a
temporary register to reduce one read operation. Additionally, other
uops, except ones_sum, reduce the basemask calculation and the right
shift basemask operation.
fix vpermtest to fit new vcompress

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Decode: fix bug of vecWen, add assertion for write two regfile in one uop

Backend: change VCONFIG_IDX to Vl_IDX

Decode: add V0_IDX Vl_IDX

Decode: remove no use vecRat addr

Rename: v0 vl split

Decode: v0 vl split

vtype: fix bug when vsetvl instruction's rd and rs1 are x0 (#3039)

* fix uop split bug for vsetvl when rd and rs1 are 0, the first uop use
wrong source register
* fix vtype writeback logic, add mu

vtype: fix bug when vsetvl instruction's rd and rs1 are x0 (#3039)

* fix uop split bug for vsetvl when rd and rs1 are 0, the first uop use
wrong source register
* fix vtype writeback logic, add mux to choose vtype from intExu or
vfExu

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vtype: fix vtype update when redirect is in next cycle of vset commit (#3014)

vtype: fix walk vtype value after using snapshot and the redirect siganl for vtype

vtype: add snapshot to store the vtype value in vtypebuffer and restore it when walk

rv64v: set vma instructions always depend on oldvd (#3000)

vma instruction will use 3 operations to calculate result, it cannot set the third operation to a dontcare value

DecodeUnitComp: after fp-split, i2v uops should write vector reg and do not use (VCONFIG) logic reg as temp reg

DecodeStage: fix canAccept: when either rename or complex decoder can receive instructions, decode can receive instructions from ibuffer

DecodeUnitComp: srcType(2) of all i/f to vector move uops should not be vp

vtype: fix walk vtype and commit vtype update when state is special walk

rv64v: set vector segment indexed store instrucion's vecwen to false

rv64v: fix uop split for vector segment indexed load/store

Decode: fix vector load/store instruction judgment

Backend: split vector load/store FuType by is segment or not

Decode: remove fix frflags

* Since this optimization has not been used, we remove it to make correct hand-shake between rename and dispatch