fix(csr): filter out Read-Only CSR in regOut (#4412)

fix(criticalError): Stop counting `wfi_cycles` when disable `wfiResume` (#4623)

* The precondition for `commitStuck_overflow` to trigger a critical
error is that `WFI` resumes after 1M(2^20) cycles.

fix(intr,difftest): add interrupt delegate (#4516)

fix(vstopi): fix vstopi result selection

* AIA Spec:
* Ties in nominal priority are broken as usual by the default priority
* order from Table 8, unless hvictl fields VTI = 1 and IID ≠ 9
* (last ite

fix(vstopi): fix vstopi result selection

* AIA Spec:
* Ties in nominal priority are broken as usual by the default priority
* order from Table 8, unless hvictl fields VTI = 1 and IID ≠ 9
* (last item in the candidate list above), in which case
* default priority order is determined solely by hvictl.DPR.

* If bit IPRIOM (IPRIO Mode) of hvictl is zero, IPRIO in vstopi is 1;
* else, if the priority number for the highest-priority candidate
* is within the range 1 to 255, IPRIO is that value; else, IPRIO
* is set to either 0 or 255 in the manner documented for stopi
* in Section 5.4.2.

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fix(xtopi): fix m/stopi.IRPIO generation conditions

* If all bytes of the supervisor-level iprio array are read-only zeros,
* a simplified implementation of field IPRIO is allowed in which
* its val

fix(xtopi): fix m/stopi.IRPIO generation conditions

* If all bytes of the supervisor-level iprio array are read-only zeros,
* a simplified implementation of field IPRIO is allowed in which
* its value is always 1 whenever stopi is not zero.
*
* We are configurable and do not need to simplify the implementation.

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fix(xiselect): set the minimum range for xiselect (#4594)

The miselect register implements at least enough bits to support all
implemented miselect values.
The siselect register will support the val

fix(xiselect): set the minimum range for xiselect (#4594)

The miselect register implements at least enough bits to support all
implemented miselect values.
The siselect register will support the value range 0..0xFFF at a
minimum.
The vsiselect register will support the value range 0..0xFFF at a
minimum.

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fix(rename): fix Csrr format (#4605)

fix(csr): fix trap handle bundle format (#4579)

fix(exceptionGen): clear isEnqExcp when older or curr wb exception coming (#4570)

feat(PMA, CSR): support PMA CSR configurable (#4233)

fix(vstopi): remove SEI from Candidate 4 (#4533)

* if hvictl.VTI = 0:
* the highest-priority pending-and-enabled major interrupt indicated
* by vsip and vsie other than a supervisor external interru

fix(vstopi): remove SEI from Candidate 4 (#4533)

* if hvictl.VTI = 0:
* the highest-priority pending-and-enabled major interrupt indicated
* by vsip and vsie other than a supervisor external interrupt(code 9),
* using the priority numbers assigned by hviprio1 and hviprio2.
*
* A hypervisor can choose to employ registers hviprio1 and hviprio2
* when emulating the (virtual) supervisor-level iprio array accessed
* indirectly through siselect and sireg (really vsiselect and vsireg)
* for a virtual hart. For interrupts not in the subset supported by
* hviprio1 and hviprio2, the priority number bytes in the emulated
* iprio array can be read-only zeros.

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fix(CSR): remove useless logic of `mIRVec` (#4553)

refactor(DFT): refactor `DFT` IO (#4530)

fix(decode): block the vector decode until vsetvl has committed (#4535)

timing(StoreMisalignBuffer): fix misalign buffer enq timing (#4493)

* a misalign store will enqueue misalign buffer at s1, and revoke if it
needs at s2

fix(Svinval): remove assert related to Svinval extension in ROB (#4519)

The RISC-V manual says that:
> In typical usage, software will invalidate a range of virtual
> addresses in the addresstransla

fix(Svinval): remove assert related to Svinval extension in ROB (#4519)

The RISC-V manual says that:
> In typical usage, software will invalidate a range of virtual
> addresses in the addresstranslation caches by executing an
> SFENCE.W.INVAL instruction, executing a series of SINVAL.VMA,
> HINVAL.VVMA, or HINVAL.GVMA instructions to the addresses (and
> optionally ASIDs or VMIDs) in question, and then executing an
> SFENCE.INVAL.IR instruction.

Some additional information was obtained through
https://github.com/riscv/riscv-isa-manual/issues/1936

However, other instructions may still appear between SFENCE.W.INVAL and
SFENCE.INVAL.IR.
> Translation of any memory accesses during that sequence are subject to
> the usual uncertainty as to which translation (among old and new ones)
> is used.

Moreover, these memory accesses are not entirely unpredictable either.
> Each subsequent memory access will unpredictably use either the old
> translation or the new translation. Other behaviors can't occur.

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fix(difftest): fix sync aia event valid (#4517)

fix(CSR): use GEILEN from IMSICParams (#4520)

feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument

feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument
2. Run with "--dump-db --dump-select-db lifetime", then get the database
3. Instruction lifetime visualize run "python3 scripts/perfcct.py
"the-db-file-path" -p 1 -v | less"
4. Analysis script now is in XS-GEM5 repo, see
https://github.com/OpenXiangShan/GEM5/blob/xs-dev/util/ClockAnalysis.py

How it works:
1. Allocate one unique tag "seqNum" like GEM5 for each instruction at
fetch stage
2. Passing the "seqNum" in each pipeline
3. Recording perf data through the DPIC interface

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feat(AIA): integrate ChiselAIA again (#4509)

feat(backend): make wfi timeout configurable (#4491)

feat(Sram): add `SRAM_CTL` interface (#4474)

* add `SRAM_CTL` interface for SRAMTemplate
* use `SRAM_WITH_CTL` to enable,
e.g. `make sim-verilog CONFIG=KunminghuV2Config RELEASE=1
SRAM_WITH_CTL=

feat(Sram): add `SRAM_CTL` interface (#4474)

* add `SRAM_CTL` interface for SRAMTemplate
* use `SRAM_WITH_CTL` to enable,
e.g. `make sim-verilog CONFIG=KunminghuV2Config RELEASE=1
SRAM_WITH_CTL=1`

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fix(topdown): when instr fused, take it as NoStall (#4475)

fix(FusionDecoder): tie output to false when disabled (#4456)

fix(difftest, CSR): sync non-reg interrupt pending right after reset (#4449)